MPM3610A Datasheet by Monolithic Power Systems Inc.

PG MPM3610A PGND Mam: EST sw OUT FB NC “H < 3="" 3vi1="" qavout="" r1="" 75k="" r2="" 24k="" effi="" iencv="" 1%)="" efficiency="" vs.="" load="" current="" voma="" 3v="" v|n="5V" load="" current="" (a)="">

MPM3610A

21V/1.2A DC/DC Module

Synchronous Step-Down Converter

with Integrated Inductor

MPM3610A Rev. 1.0 www.MonolithicPower.com 1

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The Future of Analog IC Technology

DESCRIPTION

The MPM3610A is a synchronous rectified,

step-down module converter with built-in power

MOSFETs, inductor, and two capacitors. It

offers a very compact solution, requires only 5

external components to achieve a 1.2A

continuous output current with excellent load

and line regulation over a wide input supply

range and provides fast load transient response.

Full protection features include over-current

protection and thermal shut-down.

MPM3610A eliminates design and

manufacturing risks while dramatically

improving time-to-market.

The MPM3610A is available in a space-saving

QFN20 (3mmx5mmx1.6mm) package.

FEATURES

• 4.5V-to-21V Operating Input Range

• 1.2A Continuous Load Current

• 90m/40m Low RDS(ON) Internal Power

MOSFETs

• Integrated Inductor

• Integrated VCC and Bootstrap Capacitors

• Power Save Mode at Light Load

• Power Good Indicator

• OCP Protection and Hiccup

• Thermal Shutdown

• Output Adjustable from 0.8V

• Available in QFN20 (3x5x1.6mm) Package

• Total solution size 6.7mm x7.3mm

APPLICATIONS

• Industrial Controls

• Medical and Imaging Equipment

• Telecom and Networking Applications

• LDO Replacement

• Space and Resource-limited Applications

All MPS parts are lead-free and adhere to the RoHS directive. For MPS green

status, please visit MPS website under Products, Quality Assurance page.

“MPS” and “The Future of Analog IC Technology” are registered trademarks of

Monolithic Power Systems, Inc.

TYPICAL APPLICATION

0

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ORDERING INFORMATION

Part Number* Package Top Marking

MPM3610AGQV QFN-20 (3mmx5mmx1.6mm) See Below

* For Tape & Reel, add suffix –Z (e.g. MPM3610AGQV–Z);

TOP MARKING

MP: MPS prefix:

Y: year code;

W: week code:

3610A: first five digits of the part number;

LLL: lot number;

M: module;

I'I'IPS' FE VCC AGND SW SW SW TOP VIEW PG EN IN NCPGNDPGND All 'NC' pins J must be leﬂl'l PGND EST NC OUT OUT OUT power anem or

MPM3610A – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR

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PACKAGE REFERENCE

ABSOLUTE MAXIMUM RATINGS (1)

VIN ................................................ -0.3V to 28V

VSW ....................................................................

-0.3V (-5V for <10ns) to 28V (30V for <10ns)

VBST ...................................................... VSW+6V

All Other Pins ............................... -0.3V to 6V (2)

Continuous Power Dissipation (TA = +25°C) (3)

............................................................ 2.7W

Junction Temperature .............................. 150°C

Lead Temperature ................................... 260°C

Storage Temperature ................. -65°C to 150°C

Recommended Operating Conditions (4)

Supply Voltage VIN .......................... 4.5V to 21V

Output Voltage VOUT ............... 0.8V to VIN*DMAX

(5)

Operating Junction Temp. (TJ). -40°C to +125°C

Thermal Resistance (6) θJA θJC

QFN-20 (3mmx5mmx1.6mm) . 46 ...... 10 ... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) About the details of EN pin’s ABS MAX rating, please refer to

page 14, Enable control section.

3) The maximum allowable power dissipation is a function of the

maximum junction temperature TJ (MAX), the junction-to-

ambient thermal resistance JA, and the ambient temperature

TA. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by PD (MAX) = (TJ

(MAX)-TA)/JA. Exceeding the maximum allowable powe

r

dissipation will cause excessive die temperature, and the

regulator will go into thermal shutdown. Internal thermal

shutdown circuitry protects the device from permanen

t

damage.

4) The device is not guaranteed to function outside of its

operating conditions.

5) In practical design, the minimum VOUT is limited by minimum

on time, 50ns on time is commonly recommended fo

r

calculating to give some margin. For output voltage setting

above 5.5V, please refer to the application information on

page 17.

6) Measured on JESD51-7, 4-layer PCB.

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ELECTRICAL CHARACTERISTICS

Vin=12V, TJ=-40°C to +125°C(7), typical value is tested at TJ=+25°C, unless otherwise noted.

Paramete

r

Symbol Condition Min Typ Max Units

Supply Current (Shutdown) Is VEN = 0V, TJ =+25°C 6.5 8 A

VEN = 0V, TJ =-40°C to +125°C 6.5 9 A

Supply Current (Quiescent) Iq VFB = 1V, TJ =+25°C 0.3 0.39 mA

VFB = 1V, TJ =-40°C to +125°C 0.3 0.44 mA

HS Switch-On Resistance HSRDS-ON V

BST-SW=5V 90 m

LS Switch-On Resistance LSRDS-ON V

CC =5V 40 m

Inductor DC Resistance LDCR 60 m

Switch Leakage SWLKG V

EN = 0V, VSW =12V 1 A

Current Limit ILIMIT Under 40% Duty Cycle 2.3 3 A

Oscillator Frequency fSW VFB=0.75V, TJ =+25°C 1600 2000 2400 kHz

VFB=0.75V, TJ =-40°C to +125°C 1500 2000 2500 kHz

Fold-Back Frequency fFB V

FB=200mV 0.3 fSW

Maximum Duty Cycle DMAX VFB=700mV, TJ =+25°C 78 83 88 %

VFB=700mV, TJ =-40°C to +125°C 77 83 89 %

Minimum On Time

(

8

)

ON_MIN 30 ns

Feedback Voltage VFB TJ =25°C 786 798 810 mV

TJ =-40°C to +125°C 782 798 814 mV

Feedback Current IFB V

FB=820mV 10 50 nA

EN Rising Threshold VEN_RISING

TJ =+25°C 1.2 1.4 1.6 V

TJ =-40°C to +125°C 1.15 1.4 1.65 V

EN Falling Threshold VEN_FALLING

TJ =+25°C 1.05 1.25 1.4 V

TJ =-40°C to +125°C 1 1.25 1.45 V

EN Input Current IEN

VEN=2V, TJ =+25°C 2 2.3 2.6 A

VEN=2V, TJ =-40°C to +125°C 1.8 2.3 2.8 A

Power Good Rising Threshold PGVTH-Hi T

J =+25°C 0.86 0.9 0.95 VFB

Power Good Falling Threshold PGVTH-LO T

J =+25°C 0.78 0.83 0.88 VFB

Power Good Rising Delay PGTD_RSING

TJ =+25°C 15 35 55 µs

TJ =-40°C to +125°C 10 35 60 µs

Power Good Falling Delay PGTD_FALLING

TJ =+25°C 40 80 125 µs

TJ =-40°C to +125°C 30 80 135 µs

Power Good Sink Current

Capability VPG Sink 1mA 0.4 V

Power Good Leakage Current IPG-LEAK V

PG=6V 1 A

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ELECTRICAL CHARACTERISTICS(continued)

Vin=12V, TJ=-40°C to +125°C, typical value is tested at TJ=+25°C, unless otherwise noted.

Paramete

r

Symbol Condition Min Typ Max Units

VIN Under-Voltage Lockout

Threshold—Rising INUVVth TJ =+25°C 3.7 3.9 4.1 V

TJ =-40°C to +125°C 3.65 3.9 4.15 V

VIN Under-Voltage Lockout

Threshold—Hysteresis INUVHYS 600 675 750 mV

VCC Regulator VCC TJ =+25°C 4.75 4.9 5.05 V

TJ =-40°C to +125°C 4.7 4.9 5.1 V

VCC Load Regulation ICC=5mA 1.5 3 %

Soft-Start Time tSS

VOUT from 10% to 90%, TJ =+25°C 0.8 1.6 2.4 ms

VOUT from 10% to 90%, TJ =-40°C

to +125°C 0.6 1.6 2.6 ms

Thermal Shutdown (8) T

SD 150 °C

Thermal Hysteresis (8) T

SD_HYS 20 °C

Notes:

7) Not tested in production. Guaranteed by over-temperature correlation.

8) Guaranteed by Characterization.

I'I'IIE' LOAD REGULATlON W.) EFFICIENCY ("/n) EFFIClENCV (%) Eff' 'ency vs. Load Current Vour:5V vw=s ? Z 9 LE 4 3 0 m 11 o < o="" (="" :12v="" 4="" load="" current="" (a)="" load="" regulation="" voma="" 3v="" ;’="" o="" z="" w="" 2="" (l="" (l="" m="" load="" current="" (a)="" eff'="" 'ency="" vs.="" load="" current="" vomn="" av="" load="" regulation="" (va)="" load="" current="" (a)="" load="" regulation="" vour:5v="" efflciencv="" (9.)="" load="" current="" (a)="" eff="" ency="" vs.="" load="" current="" vour="" 5v="" 2="" q="" e="" 4="" 3="" 0="" m="" m="" a="" (="" o="" 4="" load="" current="" (a)="" load="" regulation="" vomn="" 8v="" ;="" u="" z="" y="" 9="" (l="" (l="" m="" load="" current="" (a)="" eff'="" 'ency="" vs.="" load="" current="" v0u="" av="" v(="" :5="" load="" current="" (a)="" load="" regulation="" vomq="" 5v="" load="" current="" (a)="" efficiency="" vs.="" load="" current="" vomm="" 2v="" load="" current="" (a)="">

MPM3610A – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR

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TYPICAL CHARACTERISTICS

VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted.

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I'I'IIE' LOAD REGULATION (%) LINE REGULATION (%) CASE TEMPERATURE RISE (’0) Load Regulation Vom=1 2v LoAD CURRENT (A) Line Regulation V(N=5V to v. VOUT=3 3v VlN (VJ Case Temperature Rise vs. Load Current Vow :1 2v LOAD CURRENT (A) CURRENT LIMIT (A) EFFICIENCV (%) emmaa) Effl ency vs. Load Current VouT=1V LOAD REGULATION (%) LOAD CURRENT (A) Inductor Peak Current Limit vs. Duty Cycle CASE TEMPERATURE RISE (“5) DuTv CYCLE (%) Bode Plot IW :1 2A PHASE MARGlN(DEG) MAXIMUM vlhﬁv) FREQUENchHz) Load Regulation VouT=1V LOAD CURRENT (A) Case Temperature Rise vs. Load Current Vow =5v IN=8 LOAD CURRENT (A) Maximum VIN vs. VOUT VouTWl

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TYPICAL CHARACTERISTICS (continued)

VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted.

0

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I'IIIE' OU‘ESCENT CURRENT(mA) LEVEL (saw) Quiescent Current vs. Input Voltage VW =4 5V|a 21v. VFB=1V a Disabled Supply Current vs. Input Vokage v1N :4 5V m 21v. vEN =0v 2 1a 3 0.7 5 9 m a 0.6 g 05 a ’ . > e 0.4 i 5 EL 0.3 3 4 a 3 0.2 ﬂ 2 m 0.1 E 1 o D a a 5 1a 15 20 25 0 5 m 15 20 25 1NPUT VOLTAGEW) INPUT VOLTAGEW) Conduction-EMI Radiated-EMI lour:‘A ‘our:‘A 80 *M . .2031! mm 70 - v 1; 1m 75 wmmamm 55 {117” 3.2.4... 70 60 G5 .. 55 so —I—““‘ 50 55 " 45 50 >1 Au 1— 45 0.3 35 40 V 30 35 d 25 30 a zu 25 4 15 20 \\ 1D 15 5 1 10 D 5 -5 0 710 15m 500 w 20 10M 30M 30M 5an 501mm 200 mm mm FREQUENCY (Hz) FREQUENCV(H1) OUTPUT VOLTAGE (V) Power Save Mode Range Recommend operanng me devlce w1|hm1h1s range for ophmal power save mode m m ; m 3 e a 12 18 21 WHAT VOLTAGE (V) 15 24

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TYPICAL CHARACTERISTICS (continued)

VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted.

I'I'II'S' lnputhutpul Ripple lnputhutput Ripple Startup through Iour= 0A Inur=1-2A Input Voltage 'our: 0A WA A/‘WA ‘kl . ,. 1 .. ,. ﬂ . 3L4 .4 .4 L. «I w L‘ a 4ms/dw wens/aw 2ms/mv Startup through Shutdown through Shutdown through Input Voltage Input Voltage Input Voltage IOUT:12A IouT:DA IOUT:12A /i i Y—«m—«Jﬂ I ¥ , __/- 7‘" a V ——-I\ 2‘ 'I 'l , I '19 a3 2ms/dw ZDmsldw lms/dw Startup through Enable Startup through Enable Shutdown through Enable low: 0A IOUT=1.2A low: 0A 5 ‘ ‘ ‘ ‘ ‘ i ‘ ‘ i r“— r"— 1 l 1 l Ims/dw 1ms/dw 4UDms/dw

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TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are captured from the evaluation board discussed in the Design

Example section.VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted.

V

SW

10V/div.

V

IN

/AC

50mV/div.

V

OUT

/AC

10mV/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

IN

10V/div.

I

OUT

1A/div.

V

SW

10V/div.

V

IN

/AC

100mV/div.

V

OUT

/AC

20mV/div.

I

OUT

2A/div.

I

OUT

2A/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

IN

10V/div.

I

OUT

2A/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

EN

5V/div.

I

OUT

2A/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

EN

5V/div.

I

OUT

2A/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

EN

5V/div.

I

OUT

2A/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

IN

10V/div.

I

OUT

500mA/div.

V

SW

10V/div.

V

OUT

2V/div.

V

PG

5V/div.

V

IN

10V/div.

I

OUT

1A/div.

I'I'II'S' shutdown through Enable Short Circuit Entry Short Circuit Steady State low : 1 2A i a ﬁ VOUT I V V ZVMIV GMT V Nix I 2V/dw ﬂ" swig VF.3 7 i . swim I vPG L sz JIM EN 3 - swam @ 5V/dw 10de H l HIV/div IUY/dlvﬁ ‘ i OUT DUI meiLix/T SAIdw ZA/dw r: 100usldiv Ems/div Arms/div Load Tran nt Response 0 SAio 1.2A ii Vow/AC 50mV/dw VOUT- . ~ p, H ZVIdw Vue SVIdw mwmv a ‘ ID 1 ‘out SAIdLiJvT. SUDmA/dw ” Anus/aw maps/mu

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are captured from the evaluation board discussed in the Design

Example section.VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted.

l'l'lPﬁ’ ND m oid m hea‘ nm he m

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PIN FUNCTIONS

Package

Pin # Name Description

1 FB

Feedback. Connect to the tap of an external resistor divider from the output to AGND to

set the output voltage. The frequency fold-back comparator lowers the oscillator

frequency when the FB voltage is below 400mV to prevent current limit runaway during

a short circuit fault. Place the resistor divider as close to the FB pin as possible. Avoid

placing vias on the FB traces.

2 VCC

Internal 5V LDO output. Internal circuit integrates LDO output capacitor, so there is no

need to add external capacitor.

3 AGND

Analog Ground. Reference ground of logic circuit. AGND is internally connected to

PGND. There is no need to add external connections to PGND.

4, 5, 6 SW Switch Output. Large copper plane is recommended on pin 4, 5 and 6 for better heat

sink.

7, 8, 9 OUT Power Output. Connect the load to this pin. Output capacitor is needed.

10, 15,

19, 20 NC DO NOT CONNECT. Pin must be left floating.

11 BST

Bootstrap. Bootstrap capacitor is integrated internally. External connection is not

needed.

12, 13, 14 PGND Power Ground. Reference ground of the power device. PCB layout requires extra care.

For best results, connect to PGND with copper and vias.

16 IN

Supply Voltage. The IN pin supplies power to internal MOSFET and regulator. The

MPM3610A operates from a +4.5V to +21V input rail. Requires a low-ESR, and low-

inductance capacitor to decouple the input rail. Place the input capacitor very close to

this pin and connect it with wide PCB traces and multiple vias.

17 EN

Pull the EN pin high to enable the module. Leave it floating or connecting it to GND will

disable the module.

18 PG

Power Good Indicator. The PG pin is an open-drain output. Connect PG pin to VCC or

other voltage source through a pull up resistor (e.g. 100k). The detail PG behavior is

on Power Good Indicator Section in OPERATION.

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FUNCTIONAL BLOCK DIAGRAM

Figure 1: Functional Block Diagram

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OPERATION

The MPM3610A is a high-frequency,

synchronous, rectified, step-down, switch-mode

converter with built-in power MOSFETs,

integrated inductor and two capacitors. It offers

a very compact solution that achieves a 1.2A

continuous output current with excellent load

and line regulation over 4.5V to 21V input

supply range.

The MPM3610A has three working modes:

AAM (Advanced Asynchronous Modulation,

similar as PFM) mode, DCM (Discontinues-

Conduction Mode) and CCM (Continues-

Conduction Mode). The device will operate from

AAM mode, DCM to CCM with the load current

increasing. In some particular condition the

device will not enter AAM mode in light load

condition, refer to “Power Save Mode Range”

curve on page 8.

AAM Control Operation

In the light load condition, MPM3610A works in

AAM mode. Refer to Figure 2, the VAAM is an

internal fixed voltage when input and output

voltages are fixed. VCOMP is the error amplifier

output which represents the peak inductor

current information. When VCOMP is lower than

VAAM, the internal clock is blocked, thus the

MPM3610A skips some pulses and achieves

the light load power save. Refer to AN032 for

more detail.

The internal clock resets every time when VCOMP

is higher than VAAM. At the same time the HS-

FET(High-Side MOSFET) turns on and remains

on until VILsense reaches the value set by VCOMP.

The light load feature in this device is optimized

for 12V input applications.

Figure 2: Simplified AAM Control Logic

DCM Control Operation

The VCOMP voltage ramps up with the increasing

of the output current, when its minimum value

exceeds VAAM, the device will enter DCM. In this

mode the internal 2MHz clock initiates the PWM

cycle, the HS-FET turns on and remains on

until VILsense reaches the value set by VCOMP,

after a period of dead time, the LS-FET (Low-

Side MOSFET) will turn on and remain on until

the inductor current value decreases to zero.

The device will repeat the same operation in

every clock cycle to regulate the output voltage.

Figure 3: DCM Control Operation

CCM Control Operation

The device will enter CCM from DCM once the

inductor current no longer drops to zero in a

clock cycle. In CCM the internal 2MHz clock

initiates the PWM cycle, the HS-FET turns on

and remains on until VILsense reaches the value

set by VCOMP, after a period of dead time, the

LS-FET will turn on and remain on until the next

clock cycle starts. The device will repeat the

same operation in every clock cycle to regulate

the output voltage.

If within 83% of one PWM period, VILsense does

not reach the value set by VCOMP, the HS power

MOSFET is forced off.

Internal VCC Regulator

A 4.9V internal regulator powers most of the

internal circuitries. This regulator takes VIN and

operates in the full VIN range. When VIN

exceeds 4.9V, the output of the regulator is in

full regulation. When VIN is less than 4.9V, the

output decreases, and the part integrates

internal decoupling capacitor. No need add

external VCC output capacitor.

I'I'IPS' EN GND Zener 8.5V-typ % EN LOGIC

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Error Amplifier

The error amplifier compares the FB pin voltage

to the internal 0.798V reference (VREF) and

outputs a current proportional to the difference

between the two. This output current then

charges or discharges the internal

compensation network to form the COMP

voltage, which controls the power MOSFET

current. The optimized internal compensation

network minimizes the external component

counts and simplifies the control loop design.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at insufficient supply voltage.

The MPM3610A UVLO comparator monitors

the output voltage of the internal regulator, VCC.

The UVLO rising threshold is about 3.9V while

its falling threshold is 3.225V.

Enable Control

EN is a control pin that turns the regulator on

and off. Drive EN high to turn on the regulator;

drive it low to turn it off. An internal 870k

resistor from EN to GND allows EN to be

floated to shut down the chip.

The EN pin is clamped internally using a 6.5V

series-Zener-diode as shown in Figure 4.

Connecting the EN input pin through a pull up

resistor to the voltage on the VIN pin limits the

EN input current to less than 100µA.

For example, with 12V connected to Vin,

RPULLUP  (12V – 6.5V) ÷ 100µA = 55k.

Connecting the EN pin directly to a voltage

source without any pull-up resistor requires

limiting the amplitude of the voltage source to

6V to prevent damage to the Zener diode.

Figure 4: 6.5V Zener Diode Connection

Internal Soft-Start

The soft-start prevents the converter output

voltage from overshooting during startup. When

the chip starts, the internal circuitry generates a

soft-start voltage (SS) that ramps up from 0V to

5V. When SS is lower than REF, the error

amplifier uses SS as the reference. When SS is

higher than REF, the error amplifier uses REF

as the reference. The SS time is internally set

to 1.6ms(VOUT from 10% to 90%).

Pre-Bias Startup

The MPM3610A has been designed for

monotonic startup into pre-biased output

voltage. If the output is pre-biased to a certain

voltage during startup, the voltage on the soft-

start capacitor will be charged. When the soft-

Start capacitor’s voltage exceeds the sensed

output voltage at the FB pin, the part starts to

turn on high side and low side power switches

sequentially. Output voltage starts to ramp up

following with soft-start slew rate.

Power Good Indicator

The MPM3610A has power good (PG) output

used to indicate whether the output voltage of

the module is ready or not. The PG pin is an

open drain output. Connect PG pin to VCC or

other voltage source through a pull up resistor

(e.g. 100k). When the input voltage is applied,

the PG pin is pulled down to GND before

internal VSS>1V. After VSS>1V, when VFB is

above 90% of VREF, the PG pin will be pulled

high after 35µs delay time. During normal

operation, the PG pin will be pulled low when

the VFB drops below 83% of VREF after 80µs

delay.

When UVLO or OTP happens, the PG pin will

be pulled low immediately; When OC(Over

current) happens, the PG pin will be pulled low

when VFB drops below 83% of VREF after 80µs

delay.

Since MPM3610A doesn’t implement dedicate

output over voltage protection, the PG won’t

response to output over voltage condition.

Over-Current-Protection and Hiccup

The MPM3610A has a cycle-by-cycle over-

current limiting control. When the inductor

current peak value exceeds internal “peak”

current limit threshold, the HS-FET will turn off

and the LS-FET will turn on and remains on

until the inductor current falls below the internal

“valley” current limit threshold. The “valley”

current limit circuit is employed to decrease the

I'I'IPS' SW Cs saw

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operation frequency after the “peak” current

limit threshold is triggered. Meanwhile, the

output voltage drops until VFB is below the

Under-Voltage (UV) threshold—typically 50%

below the reference. Once UV is triggered, the

MPM3610A enters hiccup mode to periodically

restart the part. This protection mode is

especially useful when the output is dead-

shorted to ground, and greatly reduces the

average short circuit current to alleviate thermal

issues and protect the converter. The

MPM3610A exits the hiccup mode once the

over-current condition is removed.

Thermal Shutdown

Thermal shutdown prevents the chip from

operating at exceedingly high temperatures.

When the silicon’s temperature exceeds 150°C,

the whole chip is shut down. When the

temperature drops below its lower threshold,

typically 130°C, the chip is enabled again.

Floating Driver and Bootstrap Charging

An internal bootstrap capacitor powers the

floating power MOSFET driver. This floating

driver has its own UVLO protection. This

UVLO’s rising threshold is 2.2V with a

hysteresis of 150mV. The bootstrap capacitor

voltage is regulated internally by VIN through D1,

M1, C4, L1 and C2 (Figure 5). If (VBST-VSW)

exceeds 5V, U1 will regulate M1 to maintain a

5V voltage across C4.

Figure 5: Internal Bootstrap Charging Circuit

Startup and Shutdown

If both VIN and VEN exceeds its thresholds, the

chip starts. The reference block starts first,

generating stable reference voltage, and then

the internal regulator is enabled. The regulator

provides a stable supply for the remaining

circuitries.

Three events can shut down the chip: VIN low,

VEN low and thermal shutdown. During the

shutdown procedure, the signaling path is first

blocked to avoid any fault triggering. The

COMP voltage and the internal supply rail are

then pulled down. The floating driver is not

subject to this shutdown command.

Additional RC Snubber Circuit

Additional RC snubber circuit can be chosen to

damp the device’s spike and ringing voltage to

get better EMI performance.

The power dissipation of the RC snubber circuit

can be simply estimated by the formula below:

=× × 2

Loss S S IN

PfCV

Where fS is the switching frequency; Cs is the

snubber capacitor; VIN is the input voltage.

For efficiency consideration, the value of CS

should not be set too large. Commonly a 5.6

RS and a 330pF CS is recommended to

generate the RC snubber circuit.

Figure 6: Additional RC Snubber Circuit

l'l'lPﬁ’ FB 6' T R1 —|:|vour our our

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APPLICATION INFORMATION

Setting the Output Voltage

The external resistor divider sets the output

voltage (see Typical Application on page 1).

Choose R1 refer to Table 1, R2 is then given by:

OUT

R1

R2 V1

0.798V

=

−

Figure 7: Feedback Network

Table 1 lists the recommended feedback

network parameters for common output

voltages.

Table 1: Recommended Parameters For Common Output Voltages

Small Solution Size(CIN=10µF

/

0805/25V,

COUT=22µF/0805/16V)

Low

V

OUT Ripple(CIN=10µF

/

0805/25V,

COUT=2X22µF/0805/16V)

VIN

(V)

VOUT

(V)

R1

(kΩ)

R2

(kΩ)

Cf

(pF)

VOUT

Ripple

(mV)(9)

Load

Transient

(mV)(10)

R1

(kΩ)

R2

(kΩ)

Cf

(pF)

VOUT

Ripple

(mV) (9)

Load

Transient

(mV) (10)

21

5 115 22 NS 17.6 119 40.2 7.68 NS 9.4 74

3.3 102 32.4 NS 12.4 73 62 19.6 NS 7 50

2.5 102 47.5 5.6 10 48 62 29.4 5.6 5.2 31

19

5 115 22 NS 16.4 116 40.2 7.68 NS 8.8 72

3.3 102 32.4 NS 11.4 73 62 19.6 NS 6.6 51

2.5 102 47.5 5.6 9.8 51 62 29.4 5.6 5 33

16

5 115 22 NS 15.6 116 40.2 7.68 NS 7.8 69

3.3 102 32.4 NS 10.6 72 62 19.6 NS 6 53

2.5 102 47.5 5.6 9.6 52 62 29.4 5.6 4.8 36

1.8 102 82 5.6 8.6 41 62 49.9 5.6 4 30

14

5 115 22 NS 14.8 110 40.2 7.68 NS 7.4 65

3.3 102 32.4 NS 10.2 72 40.2 12.7 NS 5.6 41

2.5 75 34.8 5.6 9.4 46 40.2 18.7 5.6 4.6 34

1.8 102 82 5.6 8.4 42 62 49.9 5.6 4.2 31

1.5 158 180 5.6 7.2 44 62 69.8 5.6 3.6 30

12

5 100 19.1 NS 13.8 93 34 6.49 NS 6.4 56

3.3 75 24 NS 9.4 61 40.2 12.7 NS 5.2 40

2.5 75 34.8 5.6 9 51 40.2 18.7 5.6 4.4 34

1.8 102 82 5.6 7.8 47 47 37.4 5.6 4 29

1.5 158 180 5.6 6.6 57 47 53.6 5.6 3.4 27

1.2 158 316 5.6 6.2 51 75 147 5.6 3 32

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Table 1: Recommended Parameters For Common Output Voltages (continued)

Small Solution Size(CIN=10µF/0805/25V,

COUT=22µF/0805/16V)

Low

V

OUT Ripple(CIN=10µF/0805/25V,

COUT=2X22µF/0805/16V)

VIN

(V)

VOUT

(V)

R1

(kΩ)

R2

(kΩ)

Cf

(pF)

VOUT

Ripple

(mV) (9)

Load

Transient

(mV) (10)

R1

(kΩ)

R2

(kΩ)

Cf

(pF)

VOUT

Ripple

(mV) (9)

Load

Transient

(mV) (10)

10

5 100 19.1 NS 13.2 77 34 6.49 NS 6.2 47

3.3 75 24 NS 8.4 58 40.2 12.7 NS 4.8 40

2.5 75 34.8 5.6 8.2 51 40.2 18.7 5.6 4 34

1.8 75 59 5.6 7.2 40 47 37.4 5.6 3.6 30

1.5 102 115 5.6 6 46 47 53.6 5.6 3.2 28

1.2 102 205 5.6 5.4 45 62 124 5.6 2.8 32

1 102 402 5.6 4.8 41 82 324 5.6 2.6 36

8

5 100 19.1 NS 9.2 76 34 6.49 NS 5 48

3.3 75 24 NS 7.6 57 40.2 12.7 NS 3.8 38

2.5 75 34.8 5.6 7 48 40.2 18.7 5.6 3.4 33

1.8 75 59 5.6 6.4 42 47 37.4 5.6 3 32

1.5 75 84.5 5.6 5.4 44 47 53.6 5.6 2.8 29

1.2 75 147 5.6 5 38 47 93.1 5.6 2.6 26

1 75 294 5.6 4.6 35 56 221 5.6 2.2 29

5

3.3 75 24 NS 6 57 40.2 12.7 NS 3.4 40

2.5 75 34.8 5.6 5.8 52 40.2 18.7 5.6 3.2 32

1.8 75 59 5.6 5.2 47 47 37.4 5.6 2.8 31

1.5 62 69.8 5.6 5 41 47 53.6 5.6 2.4 30

1.2 62 124 5.6 4.6 37 47 93.1 5.6 2.2 29

1 62 243 5.6 4.4 37 47 187 5.6 2 27

Notes:

9) The output voltage ripple is tested at 1.2A output current.

10) Load transient from 0.6A to 1.2A, slew rate =0.8A/µs.

Normally output voltage is recommended to be

set from 0.8V to 5.5V. Actually it can be set

larger than 5.5V. Output voltage ripple will be

larger in this case due to larger inductor ripple

current. Additional output capacitor is needed to

reduce the output ripple voltage.

When output voltage is high, the chip’s heat

dissipation become more important, please

refer to PC Board layout guidelines on page 18

to achieve better thermal effect.

Selecting the Input Capacitor

The input current to the step-down converter is

discontinuous, therefore requires a capacitor to

supply the AC current to the step-down

converter while maintaining the DC input

voltage. Use low ESR capacitors for the best

performance. Use ceramic capacitors with X5R

or X7R dielectrics for best results because of

their low ESR and small temperature

coefficients. For most applications, use a 10µF

capacitor.

I'IIIE'

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Since C1 absorbs the input switching current, it

requires an adequate ripple current rating. The

RMS current in the input capacitor can be

estimated by:

⎟

⎠

⎞

⎜

⎝

⎛

×−×=

IN

OUT

IN

OUT

LOAD1C V

V

1

V

II

For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current.

The input capacitor can be electrolytic, tantalum

or ceramic. When using electrolytic or tantalum

capacitors, add a small, high quality ceramic

capacitor (e.g. 0.1F) placed as close to the IC

as possible. When using ceramic capacitors,

make sure that they have enough capacitance

to provide sufficient charge to prevent

excessive voltage ripple at input. The input

voltage ripple caused by capacitance can be

estimated as:

LOAD OUT OUT

IN IN

SIN

IV V

V1

fC1V V

⎛⎞

Δ= × ×−

⎜⎟

×⎝⎠

Selecting the Output Capacitor

The output capacitor (C2) maintains the DC

output voltage. Use ceramic, tantalum, or low-

ESR electrolytic capacitors. For best results,

use low ESR capacitors to keep the output

voltage ripple low. The output voltage ripple can

be estimated as:

OUT OUT

OUT ESR

S1 IN S

VV 1

V1R

fL V 8fC2

⎛⎞⎛⎞

Δ= ×− × +

⎜⎟⎜⎟

×××

⎝⎠⎝ ⎠

Where L1 is the inductor value and RESR is the

equivalent series resistance (ESR) value of the

output capacitor. L1=1H for MPM3610A.

For ceramic capacitors, the capacitance

dominates the impedance at the switching

frequency, and the capacitance causes the

majority of the output voltage ripple. For

simplification, the output voltage ripple can be

estimated as:

OUT OUT

OUT 2

IN

S1

VV

V1

V

8f L C2

⎛⎞

=×−

⎜⎟

××× ⎝⎠

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated as:

OUT OUT

OUT ESR

IN

S1

VV

V1R

fL V

⎛⎞

=×−×

⎜⎟

×⎝⎠

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MPM3610A internal compensation is optimized

for a wide range of capacitance and ESR

values.

PC Board Layout (11)

PCB layout is very important to achieve stable

operation especially for input capacitor

placement. For best results, follow these

guidelines:

1. Use large ground plane directly connect to

PGND pin. Add vias near the PGND pin if

bottom layer is ground plane.

2. The high current paths (PGND, IN and

OUT) should have short, direct and wide

traces. Place the ceramic input capacitor

close to IN and PGND pins. Keep the

connection of input capacitor and IN pin as

short and wide as possible.

3. The external feedback resistors should be

placed next to the FB pin.

4. Keep the feedback network away from the

switching node.

Notes:

11) The recommended layout is based on Typical Application

Circuits section on page 20.

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PG

EN

IN

NC

PGND

R2 R1

C2

PGND

R3

6.7mm

NC

C3

Top Layer

Bottom Layer

Figure 8: Recommend PC Board Layout

Design Example

Below is a design example following the

application guidelines for the specifications:

Table 2: Design Example

V

IN 12V

V

OUT 3.3V

IOUT 1.2A

The detailed application schematic is shown in

Figure 10. The typical performance and circuit

waveforms have been shown in the Typical

Performance Characteristics section. For more

device applications, please refer to the related

Evaluation Board Datasheets.

I'I'IPS' 12v VIN EN RA 100k PG < est="" 3="" sw="" 55-6="" 16="" out="" 7="" a="" g="" 5w1.2avput="" mpm361oa="" "="" 2="" vcc="" fb="" 18="" pg="" nc="" 170.15.19.20="" [:an="" agnd="" :="" ﬂ="" .5:="" v="" a:="" est="" 3="" sw="" mpm361oa="" m”="" 2="" vcc="" fe="" ‘8="" pg="" nc="" pgnd="" agnd="" :="" a"="" .5="" v="" b?="" est="" sw="" mpm361oa="" °”’="" 2="" vcc="" h3="" 13="" pg="" nc="" 31.15.1320="" pgnd="" agnd="" :="" ~\="" ”7="" v="">

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TYPICAL APPLICATION CIRCUITS(12)

Figure 9: Vo=5V, Io=1.2A

Figure 10: Vo=3.3V, Io=1.2A

Figure 11: Vo=2.5V, Io=1.2A

I'I'IPS' 12v VIN 1 : EST SW MPM361OA °UT VCC FB PG NC 3,15,19,20 PGND AGND V 2 ('1 n: V of EST SW MPM361OA °UT FB NC 31.15.1920 PGND AGND NC 01. 15.19.20 EST SW MPM361OA °UT VCC FE PG PGND AGND : 9‘ ., V n, 12V 1

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TYPICAL APPLICATION CIRCUITS(continued)

Figure 12: Vo=1.8V, Io=1.2A

Figure 13: Vo=1.5V, Io=1.2A

Figure 14: Vo=1.2V, Io=1.2A

I'I'IPS' VIN 12v EST SW MPM361OA °UT VCC FB PG NC 3,15,19,20 PGND AGND : ~\ 7 V

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TYPICAL APPLICATION CIRCUITS (continued)

Figure 15: Vo=1V, Io=1.2A

Notes:

12) In 12VIN to 1VOUT application condition, the HS-FET’s on time is close to minimum on time, the SW may have a little jitter, even so the

output voltage ripple is smaller than 15mV.

I'I'IPS' In! 1 ID I—I MARKING W mum J 77* IND-AREA TOP VIEW «‘ EF ‘ ‘1 SIDE VIEW ijulﬁ EL; now: 2 RECOMMENDED LAND PATTERN ECO-12W rvr BO'I'I'OM VIEW NOTE 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) SHADED AREA IS THE KEEP-OUT ZONE. ANY POE METAL TRACE AND VIA ARE NOT ALLOWED TO CONNECT TO THIS AREA ELECTRICALLY OR MECHANICALLY. 3) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 4) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 5)JEDEC REFERENCE IS M0420. 5) DRAWING IS NOT TO SCALE.

MPM3610A – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

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PACKAGE INFORMATION

QFN-20 (3mmx5mmx1.6mm)

MPM3610A Datasheet by Monolithic Power Systems Inc.

Products related to this Datasheet