AFBR-(77D13,78D13)SZ Datasheet by Foxconn OE Technologies Singapore Pte. LTD

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MicroPOD™
AFBR-77D13SZ, AFBR-78D13SZ
10 Gbps/Channel
Twelve Channel Parallel Fiber Optics Modules
Data Sheet
Description
The AFBR-77D13SZ Twelve Channel, Pluggable, Paral-
lel Fiber Optics Transmitter and AFBR-78D13SZ Twelve
Channel, Pluggable, Parallel Fiber Optics Receiver are high
performance fiber optics modules for short-range paral-
lel multi-lane data communication and interconnect ap-
plications. The high density optical modules are designed
to operate over multimode fiber systems using a nominal
wavelength of 850 nm.
The optical interface requires the user to provide a custom
designed optical turn 1×12 ribbon cable PRIZM® Light-
Turn® connector.
Applications
100GbE, 10GbE and IB-QDR/ IB-DDR/ IB-SDR
interconnects
Data Aggregation, Backplane and Proprietary Protocol
and Density Applications
High Performance and High Productivity computer
interconnects
Switch Fabric interconnects
Part Number Ordering Options
Base Part Number
Modules for use with
Flat Ribbon Jumper Cable
Transmitter AFBR-77D13SZ
Receiver AFBR-78D13SZ
MicroPOD Evaluation Board (Tx) AFBR- 77EVB
MicroPOD Evaluation Board (Rx) AFBR- 78EVB
Where:
77 = Transmitter;
78 = Receiver
Features
Compliant to IEEE 802.3ba 100GbE (100GBASE-SR10
and nPPI) per lane and compatible with 10GBASE-SR
Compliant to 12×QDR Infiniband
Operates at 10.3125 Gbps per channel with 64b/66b
encoded data for 100GbE application and with 8b/10b
for 10GbE applications. Supports 10 Gbps with 8b/10b
for IB-QDR applications
High Aggregate bandwidth: 120 Gbps per module
High density footprint: 7.8 mm × 8.2 mm × 3.9 mm size
Separate transmitter and receiver modules;
850 nm VCSEL array in transmitter; PIN array in receiver
10.3125 Gbps links up to 300 m & 400 m with OM3 &
OM4 4700 MHz∙km 50 µm MMF
Optical Interface: PRIZM™ LightTurn® optical turn 1×12
ribbon fiber connector
Electrical interface: 9×9 micro-LGA with 0.7424 mm
pitch
Low Power consumption: 3.0 W Max per Transmitter /
Receiver pair (0 °C to 70 °C operating range)
Dedicated signals for module address, module reset
and host interrupt
Two Wire Serial (TWS) interface with maskable inter-
rupt for expanded functionality including:
Individual channel functions: disable, squelch
disable, lane polarity inversion, TX eye margin
enable
A/D read back: module temperature and supply
voltages, per channel laser current and laser power,
or received power
Status: per channel Tx fault, electrical (transmitter)
or optical (receiver) LOS, and alarm flags
Programmable equalization integrated with DC
blocking caps at transmitter data input
– Programmable receiver output swing and de-
emphasis level
Field-upgradable firmware capability
0 °C to 70 °C case temperature continuous operating
range. 85 °C supported for short durations
Avago Technologies Confidential – Restricted under NDA
Patent - www.avagotech.com/patents
2Avago Technologies Confidential – Restricted under NDA
Transmitter Module
The optical transmitter module (see Figure 1) incorporates
a 12-channel VCSEL (Vertical Cavity Surface Emitting La-
ser) array, a 12-channel input buffer and laser driver, diag-
nostic monitors, control and bias blocks. The transmitter
is designed for EN-60825 and CDRH eye safety compli-
ance; Class 3R out of the module. When fully assembled
with the PRIZM LightTurn optical connector class 1M is
achieved. The Tx Input Buffer provides CML compatible
differential inputs (presenting a nominal differential in-
put impedance of 100Ω and a nominal common mode
impedance to signal ground of 25 Ω) for the high speed
electrical interface that can operate over a wide common
mode range without requiring external DC blocking ca-
pacitors. For module control and interrogation, the con-
trol interface incorporates a Two Wire Serial (TWS) inter-
face of clock and data signals and dedicated signals for
host interrupt, module address setting and module reset.
Diagnostic monitors for VCSEL bias, light output power
(LOP), temperature, both supply voltages and elapsed
operating time are implemented and results are available
through the TWS interface.
Over the TWS interface, the user can, for individual chan-
nels, control (flip) polarity of the differential inputs, de-
Figure 1. Transmitter Block Diagram
activate channels, place channels into margin mode (sys-
tem level diagnostic mode where TX OMA is reduced by
~1 dB), disable the squelch function and program input
equalization levels to reduce the effect of long PCB traces.
A reset for the control registers is available. Serial ID infor-
mation and alarm thresholds are provided. To reduce the
need for polling, the TWS interface is augmented with an
interrupt signal for the host.
Alarm thresholds are established for the monitored attri-
butes. Flags are set and interrupts generated when the
attributes are outside the thresholds. Flags are also set
and interrupts generated for loss of input signal (LOS) and
transmitter fault conditions. All flags are latched and will
remain set even if the condition initiating the latch clears
and operation resumes. All interrupts can be masked and
flags are reset by reading the appropriate flag register.
The optical output will squelch for loss of input signal un-
less squelch is disabled. Fault detection or channel deac-
tivation through the TWS interface will disable the chan-
nel. Status, alarm and fault information are available via
the TWS interface. The interrupt signal (selectable via the
TWS interface as a pulse or static level) is provided to in-
form hosts of an assertion of an alarm, LOS and/or Tx fault.
LGA Interface (81x)
Optical Interface
Din[11:0][p/n] (24) Tx Input Buffer
12 Channels
Control
Laser Driver
12 Channels
Diagnostic
Monitors
1 x 12 VCSEL Array
Bias
IO Count : 81
Power : 40
High speed : 24
Digital : 10
NC : 7
IntL (2)
SCL (2)
SDA (2)
Adr[2:0] (3)
ResetL (1)
Vcc33 (4)
Vcc25 (x)
NC (7)
Gnd (32)
3Avago Technologies Confidential – Restricted under NDA
Receiver Module
The optical receiver module (see Figure 2) incorporates a
12-channel PIN photodiode array, a 12-channel pre-am-
plifier and output buffer, diagnostic monitors, control and
bias blocks. The Rx Output Buffer provides CML compat-
ible differential outputs for the high speed electrical in-
terface presenting nominal single-ended output imped-
ances of 50Ω to AC ground and 100Ω differentially that
should be differentially terminated with 100 Ω. External
DC blocking capacitors are required. For module control
and interrogation, the control interface incorporates a
Two Wire Serial (TWS) interface of clock and data signals
and dedicated signals for host interrupt, module address
setting and module reset. Diagnostic monitors for opti-
cal input power, temperature, both supply voltages and
elapsed operating time are implemented and results are
available through the TWS interface.
Over the TWS interface, the user can, for individual chan-
nels, control (flip) polarity of the differential outputs, de-
activate channels, disable the squelch function, program
Figure 2. Receiver Block Diagram
output signal amplitude and de-emphasis and change re-
ceiver bandwidth. A reset for the control registers is avail-
able. Serial ID information and alarm thresholds are pro-
vided. To reduce the need for polling, the TWS interface is
augmented with an interrupt signal for the host.
Alarm thresholds are established for the monitored attri-
butes. Flags are set and interrupts generated when the at-
tributes are outside the thresholds. Flags are also set and
interrupts generated for loss of optical input signal (LOS).
All flags are latched and will remain set even if the condi-
tion initiating the latch clears and operation resumes. All
interrupts can be masked and flags are reset upon read-
ing the appropriate flag register. The electrical output will
squelch for loss of input signal (unless squelch is disabled)
and channel de-activation through TWS interface. Status
and alarm information are available via the TWS interface.
The interrupt signal (selectable via the TWS interface as a
pulse or static level) is provided to inform hosts of an as-
sertion of an alarm and/or LOS.
LGA Interface (81x)
Optical Interface
Din[11:0][p/n] (24) Rx Output Buffer
12 Channels
Control
Preamp
12 Channels
Diagnostic
Monitors
1 x 12 PIN Array
Bias
IO Count : 81
Power : 40
High speed : 24
Digital : 10
NC : 7
IntL (2)
SCL (2)
SDA (2)
Adr[2:0] (3)
ResetL (1)
Vcc33 (4)
Vcc25 (4)
Gnd (32)
eeeeeee
4Avago Technologies Confidential – Restricted under NDA
High Speed Signal Interface
Figure 3 shows the interface between an ASIC/SerDes and
the fiber optics modules. For simplicity, only one channel
is shown. As shown in Figure 3, the compliance points are
on the host board side of the electrical connectors. Sets
of s-parameters are defined for the transmitter and receiv-
er interfaces. The transmitter and receiver are designed,
when operating within Recommended Operating Condi-
tions, to provide a robust eye-opening at the receiver out-
puts. See the Recommended Operating Conditions and
the Receiver Electrical Characteristics for details.
Unused inputs and outputs should be terminated with
100 Ω differential loads.
The transmitter inputs support a wide common mode
range and DC blocking capacitors are not needed (inter-
nal capacitors are not shown in Figure 3). Depending on
the common mode range tolerance of the ASIC/SerDes
inputs, DC blocking capacitors may be required in series
with the receiver; in this case 100nF capacitors are recom-
mended. Differential impedances are nominally 100 Ω.
The common mode output impedance for the receiver is
nominally 25 Ω while the nominal common mode input
impedance of the transmitter is 25 Ω.
Figure 3. Application Reference Diagram
Figure 4. Transmitter Input Equalization
Transmitter Input Equalization
Transmitter inputs can be programmed for one of several
levels of equalization. See Figure 4. The default case pro-
vides a flat gain-frequency response in the inputs. Dif-
ferent levels of compensation can be selected to equal-
ize skin-effect losses across the host circuit board. See Tx
Memory Map 01h Upper Page section addresses 228 - 233
for programming details.
ASIC/SerDes
FO Tx (1 of 12 Lanes)
Host Board Electrical Interface
- Compliance Points -
FO Rx Electrical Interface
FO Rx (1 of 12 Lanes)
FO Tx Electrical Interface
SDD22
SCC22
SCC11
SDD11
SCD11
SDC22
CAC
CAC
100
50
50
100
50
50
Frequency
Gain
No Equalization
Maximum Equalization
5Avago Technologies Confidential – Restricted under NDA
Receiver Output Amplitude and De-emphasis
Receiver outputs can be programmed to provide several
levels of amplitude and de-emphasis. See Figure 5 for de-
emphasis definition. The user can program for peak-to-
peak amplitude and then a de-emphasis level. If zero de-
emphasis is selected, then the signal steady state equals
the peak-to-peak level. For other levels of de-emphasis
the selected de-emphasis reduces the steady-state from
the peak-to-peak level. The change from peak-to-peak
level to steady-state occurs within a bit time. See Rx Mem-
ory Map 01h Upper Page section addresses 228 - 233 for
amplitude programming details and addresses 234 – 239
for de-emphasis programming details.
Figure 5. Definition of De-emphasis and Steady State
Figure 6. Link Model test point definitions
Control Signal Interface
The control interface includes dedicated signals for ad-
dress inputs, interrupt output and reset input, and bidi-
rectional clock and data lines, for a two-wire serial access
(TWS interface) to control, status and information regis-
ters. The TWS interface is compatible with industry stan-
dard two-wire serial protocol. The MicroPOD module is
implemented as a slave device. Signal and timing charac-
teristics are further defined in the Control Characteristics
and Control Interface and Memory Map sections.
The registers of the serial interface memory are defined in
the Control Interface and Memory Map section.
1 bit
Data 10 000 01 1 1 1
Output
Voltage
De-Emphasis (DE)
Steady-State (SS)
De-Emphasis % = (DE/SS)(100%)
ASIC
MicroPOD TX
MicroPOD RX
ASIC
TP0 TP1 TP1a
TP2 TP3
TP4a TP4 TP5
Electrical
Connector
Electrical
Connector
Optical Patch Cord
Link Model and Reference Channel
Performance specifications for the MicroPOD modules based on IEEE 802.3ba 100GBASE-SR10.
6Avago Technologies Confidential – Restricted under NDA
Absolute Maximum Ratings
Stress in excess of any of the individual Absolute Maximum Ratings can cause immediate catastrophic damage to the
module even if all other parameters are within Recommended Operation Conditions. It should not be assumed that
limiting values of more than one parameter can be applied to the module concurrently. Exposure to any of the Absolute
Maximum Ratings for extended periods can adversely affect reliability.
The TX and RX modules are not hermetically packaged, exposure to a condensing environment is not allowed.
Notice that both TX and RX Cu blocks (heat sink) are electrically connected to signal GND. There is no separated module
case GND. Care must be taken when handling the modules.
Parameter Symbol Min Max Units Notes
Storage Temperature Ts-40 85 °C
Absolute Maximum Operating Temperature -20 85 °C Note 1
2.5 V Power Supply Voltage Vcc25 -0.5 3.0 V
3.3 V Power Supply Voltage Vcc33 -0.5 4.0 V
Data Input Voltage – Single Ended -0.5 Vcc33+0.5,
Vcc25+0.5,
4.0
V Least of the three
Data Input Voltage – Differential |VDIp - VDIn| 1.0 V Note 2
Control Input Voltage Vi-0.5 Vcc33+0.5, 4.0 V Note 3
Control Output Current Io-20 20 mA
Relative Humidity RH 5 95 % Note 4
Receiver Damage Threshold Rx_PMAX +4 dBm
Notes:
1. The position for case temperature measurement is shown in Figure 22. Electro-optical specifications are not guaranteed outside the recommended
operating temperature range. Operation above the Absolute Maximum Case Temperature for extended periods may adversely affect reliability.
2. This is the maximum voltage that can be applied across the differential inputs without damaging the input circuitry.
3. The maximum limit is the lesser of Vcc + 0.5 V or 4.0 V. SDA and SCL may be forced to <=4V for any Vcc33 value. Note that both 1.2V CMOS and LVTTL
logic is tolerant of voltage up to Vcc33+0.5.
4. Exposure to a condensing environment is not allowed.
7Avago Technologies Confidential – Restricted under NDA
Recommended Operating Conditions
Recommended Operating Conditions specify parameters for which the optical and electrical characteristics hold unless
otherwise noted. Optical and electrical characteristics are not defined for operation outside the Recommended Oper-
ating Conditions, reliability is not implied and damage to the module may occur for such operation over an extended
period of time.
Parameter Symbol Min Typ Max Units Reference
Case Temperature Tc0 70 °C Note 1
Case Temperature (short term) Tc_ext 70 85 °CNote 2
2.5 V Power Supply Voltage Vcc25 2.375 2.5 2.625 V Note 3
3.3 V Power Supply Voltage Vcc33 3.135 3.3 3.465 V
Signal Rate per Channel (rates < 3.125 Gb/s
must be 8b/10b encoded)
1.25 10.3125 GBd Note 4
Host Electrical Compliance Per IEEE 802.3ba-2010 TP1a and
TP4 nPPI specifications for host
Control Input Voltage High Vih 2.3 3.6 V
Control Input Voltage Low Vil -0.3 0.4 V
Two Wire Serial Interface Clock Rate 400 kHz
Two Wire Serial Interface Write Cycle Time
(up to 2 sequential bytes)
tWC 100 ms
Reset Pulse Width tRSTL PW 10 µs
Power Supply Noise 100 mVpp Note 5, 500 Hz
to 5.4 GHz
Receiver Differential Data Output Load 100 Figure 3
AC Coupling Capacitors –
Receiver Data Outputs
Cac 0.1 µF Note 6,
Figure 3
Fiber Length: 4700 MHz∙km 50 µm MMF (OM4)
2000 MHz∙km 50 µm MMF (OM3)
0.5
0.5
400
300
m
m
Note 7
Fiber Pull Force (long duration**) 0.98 N
Fiber Pull Force (short duration*) 2.2 N
PRIZM Insertion Force (short duration*) 40 N
* Short duration is <15 seconds.
** Long duration (>5 minutes), exceeding this force long term could cause the optical light output power to drop or Rx sensitivity to diminish, which
is not recoverable.
Notes:
1. Continuous operation above 70 °C should be avoided in order not to degrade reliability. The position for case temperature measurement is shown
in Figure 22.
2. Short term is defined per section 4.1.2 of Telcordia GR-63-CORE Issue 3, March 2006 and corresponds to a period of not more than 96 consecutive
hours and a total of not more than 15 days in 1 year (This refers to a total of 360 hours in any given year, but no more than 15 occurrences during
that 1-year period).
3. There are no restrictions to the 2.5 V and 3.3 V power supply sequencing.
4. Higher data rates are possible. For further details, contact your Avago sales representative.
5. Power Supply Noise is defined as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power
supply filter with the module and recommended filter in place. Voltage levels including peak-to-peak noise are limited to the recommended
operating range of the associated power supply. See Figure 8 for recommended power supply filters.
6. For data pattern with restricted run lengths and disparity, e.g., 8b10b, smaller value capacitors may provide acceptable results.
7. Channel insertion loss includes 3.5 dB/km attenuation, 1.5 dB connector loss and 0.3 dB modal noise penalty allocations.
8Avago Technologies Confidential – Restricted under NDA
Transmitter Electrical Characteristics*
The following characteristics are defined over the Recommended Operating Conditions from 0 °C to 70 °C, unless oth-
erwise noted. Typical values are for Tc = 40 °C, Vcc33 = 3.3 V and Vcc25 = 2.5 V. Note: The TX output performance is only
guaranteed when measured with a differential input that meets the recommended operating conditions. A link driven
with a single-ended signal will degrade the jitter performance.
Parameter Symbols Min Typ Max Units Reference
Power Consumption (Max EQ) 1.2 1.6 W Note 1
Power Supply Current - Vcc25 280 365 mA Note 2
Power Supply Current - Vcc33 105 185 mA Note 3
Differential Input Impedance 85 100 115 Informative
LOS Assert Threshold: Tx Data Input
Differential Peak-to-Peak Voltage Swing
ΔVDI PP LOS 50 mVpp Informative
LOS De-Assert Threshold: Tx Data Input
Differential Peak-to-Peak Voltage Swing
ΔVDI PP LOS 210 mVpp Note 4,
Informative
LOS Hysteresis 0.5 4 dB
Power On Initialization Time tPWR INIT 350 2000 ms Note 5
Parameter Test Point Min Typ Max Units Reference
Single ended input voltage tolerance TP1a -0.3 4.0 V Note 6
AC common mode input voltage tolerance TP1a 15 mV RMS
Differential input return loss TP1 dB Note 7, 10 MHz to 11.1 GHz
Differential to common-mode
input return loss
TP1 10 dB 10 MHz to 11.1 GHz
J2 Jitter tolerance TP1a 0.17 UI Defined in 802.3ba
J9 Jitter tolerance TP1a 0.29 UI Defined in 802.3ba
Data Dependent Pulse Width Shrinkage
(DDPWS) tolerance
TP1a 0.07 UI Defined in 802.3ba
Eye Mask Coordinates:
X1, X2,
Y1, Y2
TP1a
0.11, 0.31
95, 350
UI
mV
Note 8, Hit Ratio = 5x10-5
* For control signal timing including Adr[2:0], IntL, ResetL, SCL and SDA see Control Characteristics: Transmitter/Receiver.
Notes:
1. Max power is 1.7 W above 70 °C, to 85 °C case temperature.
2. Supply current includes that of all Vcc25 contacts.
3. Supply current includes that of all Vcc33 contacts. Max current is 210 mA above 70 °C, to 85 °C case temperature.
4. Tx data input must conform to IEEE 802.3ba-2010 TP1a electrical host compliance specification.
5. Power On Initialization Time is the time from when the supply voltages reach and remain above the minimum Recommended Operating Conditions
to the time when the module enables TWS access. The module at that point is fully functional.
6. Referred to TP1 signal common; The single-ended input voltage tolerance is the allowable range of the instantaneous input signals.
7. From 10 MHz to 11.1 GHz, the magnitude in decibels of the module differential input return loss at TP1 and the host differential output return loss
at TP1a shall not exceed the limit given in Equation
Return_loss (ƒ) ≥ 12 – 2√(f) 0.01 ≤ f < 4.1 dB
≥ 6.3 – 13log10(f/5.5) 4.11 ≤ f < 11.1 dB
Return_loss (ƒ) is the return loss at frequency f
f is the frequency in GHz
8.
Tx Electrical Eye Mask Coordinates (TP1a) at Hit ratio 5 x 10-5 hits per sample
0
-Y1
Y1
01-X1
X1 1
Time (UI)
Differential amplitude (mV)
Y2
-Y2
X2 1-X2
9Avago Technologies Confidential – Restricted under NDA
Receiver Electrical Characteristics
The following characteristics are defined over the Recommended Operating Conditions from 0 °C to 70 °C, unless oth-
erwise noted. Typical values are for Tc = 40 °C, Vcc33 = 3.3 V and Vcc25 = 2.5 V. Note: The RX output performance is only
guaranteed when measured with a differential output that meets the recommended operating conditions. A link driven
with a single-ended signal will degrade the jitter performance.
Parameter Test Point Min Typ Max Units Reference
Power Consumption 1.1 1.4 W Note 1
Power Supply Current (Vcc25) -
@ Default De-emphasis / Default output swing
350 425 mA Note 2
Power Supply Current (Vcc33) -
@ Default De-emphasis / Default output swing
48 90 mA Note 3
Power Supply Current (Vcc25) -
@ Max De-emphasis/Max output swing
430 525 mA Note 2
Power Supply Current (Vcc33) -
@ Max De-emphasis/Max output swing
48 90 mA Note 3
Data Output Differential Peak-to-Peak Voltage Swing
(Default De-emphasis)
TP4 400 500 600 mVpp Note 4, 100 Load
(default setting)
Data Output Common Mode Voltage TP4 2.0 2.540 V Over Amplitude
Range
AC common-mode output voltage (RMS) TP4 7.5 mV
Termination mismatch at 1 MHz TP4 5 %
Differential Output Impedance TP4 85 115 Informative
Differential Output Return Loss, 10M-11.1 GHz TP4 dB Note 5
CM to Differential Mode Conversion, 0.1G-11.1 GHz TP4 dB Note 6
Power On Initialization Time 288 2000 ms
Output transition time (20% to 80%) TP4 28 ps
J2 Jitter Output TP4 0.42 UI Defined in 802.3ba
J9 Jitter Output TP4 0.65 UI Defined in 802.3ba
Data Dependent Pulse Width Shrinkage TP4 0.34 UI Defined in 802.3ba
Inter-channel Skew TP4 11 ns
Inter-channel Skew Variation TP4 100 ps Note 7
Specification Values
Eye Mask Coordinates: X1, X2,
Y1, Y2
TP4 0.29, 0.5
150, 425
UI
mV
Note 8,
Hit Ratio = 5x10-5
Y2
Differential Amplitude [mV]
-Y2
Y1
-Y1
0
Normalized Time [UI]
0 X1 X2 1-X1 1.0
Rx Electrical Eye Mask Coordinates (TP4) at Hit ratio 5 x 10-5 hits
per sample
Notes:
1. Max conditions include default output amplitude and de-emphasis programming.
2. Supply current includes that of all Vcc25 contacts.
3. Supply current includes that of all Vcc33 contacts.
4. See section on page 47 “Receiver Output Amplitude Control Code Description
for range of voltages defined in the receiver upper page 01h, address range 228
to 233. Data outputs are CML compatible. Data Output Differential Peak to Peak
Voltage Swing is defined as follows: ΔVDO pp = ΔVDOH - ΔVDOL where ΔVDOH
= High State Differential Data Output Voltage and ΔVDOL = Low State Differential
Data Output Voltage. Output voltage swing is adjustable via TWS interface.
5. From 10MHz to 11.1 GHz. The magnitude in decibels of the module differential
output return loss at TP4 and the host differential input return loss at TP4a shall
not exceed the limit given in Equation
Return_loss (f) 12 -2√(f) 0.01 ≤ f < 4.1 dB
≥ 6.3 - 13log10(f/5.5) 4.11 ≤ f < 11.1 dB
6. From 10 MHz to 11.1 GHz. The magnitude in decibels of the host common mode
output return loss at TP4 shall not exceed the limit given in Equation:
Return_loss (f) ≥ 7 - 1.6f 0.01 ≤ f < 2.5 dB
≥ 3 2.5 ≤ f < 11.1 dB
f is the frequency in GHz
7. Inter-Channel Skew is defined for the condition of equal amplitude, zero ps skew
input signals at TP1a.
8.
n \l V\xx\!\: m . wavahxed W W \ntzrvah
10 Avago Technologies Confidential – Restricted under NDA
Transmitter Optical Characteristics [1]
The following characteristics are defined over the Recommended Operating Conditions from 0 °C to 70 °C, unless oth-
erwise noted. Typical values are for Tc = 40 °C, Vcc33 = 3.3 V and Vcc25 = 2.5 V. Test point = TP2. Note that the TX output
performance is only guaranteed with a differential input that meets the recommended operating conditions. A link
driven with a single-ended signal will degrade the jitter performance.
Parameter Symbol Min Typ Max Units Reference
Center Wavelength λc840 850 860 nm
RMS spectral width 0.35 0.65 nm Note 2
Average launch Power, each lane PO AVE -7.6 2.4 dBm
Output Optical Power: Disabled PO OFF -30 dBm
Extinction Ratio ER 3 dB
Optical Modulation Amplitude, each lane OMA -4.3 2.4 dBm Note 3
Output Power (Squelched OMA) -2.4 dBm AC Squelch
Tx Mask Margin Tx_MM 10%
Difference in launch power between any two
lanes (OMA)
4 dB
Peak power, each lane 4 dBm
Launch Power in OMA minus TDP, each lane Po - TDP -6.5 dBm
Transmitter and Dispersion Penalty, each lane TDP 3.5 dB
Optical return loss tolerance 12 dB
Encircled flux ≥ 86% at 19 μm,
≤ 30% at 4.5 μm
Note 4
Specification Values
Eye mask coordinates: X1, X2, X3
Y1, Y2, Y3
0.23, 0.34, 0.43
0.27, 0.35, 0.4
UI Note 5, Hit ratio =
5x10-5 per sample
Power On Initialization Time Tx Outputs tPWR INIT 350 2000 ms
Reset De-assert Re-initialization Time Tx
Outputs
tRSTL OFF 350 2000 ms
Output Disable Assert Time for Fault tDIS ON 9 100 ms
Output Squelch Assert Time for LOS tSQ ON 52 80 µs
Output Squelch De-assert Time for LOS tSQ OFF 49 80 µs
Notes:
1. These optical specifications are dependent upon the performance of the PRIZM LightTurn to cable assembly, which assumes a maximum of 2 dB
insertion loss. More details are provided on the PRIZM LightTurn cable assembly specification. Please contact your Avago sales representative to
receive this specification.
2. RMS spectral width is the standard deviation of the spectrum.
3. Output of user provided fiber connector. Even if the TDP<0.9 dB, the OMA must exceed this minimum value. Power exceeds IEEE802.3ae but Avago
SFP+ transceivers are compatible with this higher receiver input power. Note the possibility of high optical power DMI alarms on SFP+ Receivers
4. Compliance assured up to 10.3125 Gbps.
Transmitter eye mask definitions (TP2) at Hit ratio 5 x 10-5 hits per sample
Mask Coordinates
X1 = 0.23
X2 = 0.34
X3 = 0.43
Y1 = 0.27
Y2 = 0.35
Y3 = 0.40
11 Avago Technologies Confidential – Restricted under NDA
Receiver Optical Characteristics [1]
The following characteristics are defined over the Recommended Operating Conditions from 0 °C to 70 °C, unless oth-
erwise noted. Typical values are for Tc = 40 °C, Vcc33 = 3.3 V and Vcc25 = 2.5 V.
Parameter Test Point Min Typ Max Units Reference
Optical Modulation Amplitude (OMA), each lane TP3 +3 dBm
Stressed Sensitivity (OMA), each lane TP3 -5.4 dBm Note 2
Receiver Sensitivity (OMA) TP3 -12 dBm Informative
Operating Center Wavelength TP3 840 860 nm
Receiver Reflectance TP3 -12 dB
Peak Power, each lane TP3 +4 dBm
Output Rise/Fall time (20-80%) TP3 25 40 50 ps Note 3
LOS to Data Output Squelch Assert Time TP3 80 µs Note 4
Data Output Squelch De-assert Time TP3 80 µs Note 5
LOS ASSERT Threshold (OMA) TP3 -30 -14 dBm
LOS De-ASSERT Threshold (OMA) TP3 -12.4 -8 dBm
LOS Hysteresis TP3 0.5 1.6 dB
Notes:
1. These optical specifications are dependent upon the performance of the PRIZM LightTurn cable assembly, which assumes a maximum of 2 dB
insertion loss. More details are provided on the PRIZM LightTurn cable assembly specification. Please contact your Avago sales representative to
receive this specification.
2. Measured with conformance test signal at TP3 for BER = 10e-12.
3. These are unfiltered rise and fall times without de-emphasis measured between the 20% and 80% levels using a 500 MHz square wave test pattern.
Impairments in measurements due to the test system are removed. Specifications are for information only.
4. This is the module response time from fall of Rx input to less than Rx input LOS threshold to squelch of Rx outputs.
5. This is the module response time from rise of Rx input to greater than Rx input LOS threshold to resumption of Rx outputs.
100GBASE-SR10 Illustrative Link Power Budgets
Parameter OM3 OM4 Units Reference
Effective Modal Bandwidth at 850 nm 2000 4700 MHz•km
Launch Power in OMA minus TDP, each lane -6.5 dBm
Transmitter and Dispersion Penalty, each lane 3.5 dB
Receiver Sensitivity (OMA) -11.3 dBm
Power Budget (for maximum TDP) 8.3 dB
Operating Distance 0.5 to 100 0.5 to 150 m
Channel Insertion Loss 1.9 1.5 dB
Allocation for Penalties (for max. TDP) 6.4 6.5 dB
Unallocated Margin 0 0.3 dB
Additional Insertion Loss Allowed 0 dB
12 Avago Technologies Confidential – Restricted under NDA
Regulatory Compliance Table
Feature Test Method Performance
Electrostatic Discharge
(ESD) to the Electrical
Contacts
JEDEC Human Body Model (HBM)
(JESD22-A114-B)
Transmitter and Receiver modules withstand
minimum 1000 V on all pins.
JEDEC Machine Model (MM)
(JESD22-A115-A)
Transmitter and Receiver modules withstand
minimum 50 V on all pins.
Immunity Variation of EN 61000-4-3 Typically minimum effect from a 10 V/m field
swept from 80 MHz to 1 GHz applied to the mod-
ule without a chassis enclosure.
Laser Eye Safety and
Equipment Type Test-
ing
EN 60825-1:2007
CFR21 section 1040
Pout: IEC AEL and US FDA CDRH Class 3R* without
optical connector, Class 1M with optical connec-
tor.
CDRH Accession Number: 1020008-001
TUV Certificate Number: R72131700
Component Recogni-
tion
Underwriters Laboratories and Canadian Standards
Association Joint Component Recognition for Infor-
mation Technology Equipment including Electrical
Business Equipment
UL File Number: E173874
RoHS Compliance
(RoHS Directive
2002/95/EC issued
January 27, 2003)
BS EN 1122:2001 Mtd B by ICP for Cadmium, EPA
Method 3051A by ICP for Lead and Mercury, EPA
Method 3060A and 7196A by UV/Vis Spectropho-
tometry for Hexavalent Chromium. EPA Method
3540C/3550B by GC/MS for PPB and PBDE
BS EN method by ICP and EPA methods by ICP, UV/
Vis Spectrophotometry and GC/MS.
Less than 100 ppm of cadmium,
Less than 1000 ppm lead, mercury, hexavalent
chromium, polybrominated biphenyls, and poly-
brominated biphenyl esters.
The following regulatory compliance depends on customer system design. It is the customers responsibility to guaran-
tee the performance at the system level.
Feature Test Method Performance
Electrostatic Discharge (ESD) to
Optical Connector Receptacle
Variation of IEC 61000-4-2 Not applicable.
Actual performance dependent on user system design.
Electromagnetic
Interference (EMI)
FCC Part 15 CENELEC EN55022
(CISPR 22A) VCCI Class 1
Not applicable.
Actual performance dependent on enclosure design.
Immunity Variation of IEC 61000-4-3 Not applicable.
Actual performance dependent on enclosure design.
13 Avago Technologies Confidential – Restricted under NDA
WARNING:
CAUTION! Use of controls or adjustments or performance of procedures other than
those specified herein may result in hazardous radiation exposure
CAUTION! Laser Class 3R for laser module assembly without fiber optic cable attach-
ment.
INVISIBLE LASER RADIATION, AVOID DIRECT EYE EXPOSURE!
CLASS 3R LASER PRODUCT WITHOUT OPTIC CABLE ASSEMBLY
IEC IEC60825-1:2007
COMPLIES WITH 21 CFR 1040.10 AND 1040.11
EXCEPT FOR DEVIATIONS PERSUANT TO LASER NOTICE NO. 50, DATED JUNE 24, 2007
WARNING:
CLASS 1 LASER PRODUCT
CAUTION! Laser Class 1 Classification for laser module assembly including fiber
optic cable attachment. Safe to view laser output with the naked eye or with the
aid of typical magnifying optics (e.g., telescope or microscope).
INVISIBLE LASER RADIATION, DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS.
CLASS 1 LASER PRODUCT WITH OPTIC CABLE ASSEMBLY.
Note: Standard used for classification: EN 60825-1:2007
14 Avago Technologies Confidential – Restricted under NDA
Signal Name Signal Description I/O Type
Adr[2:0] TWS Module Bus Address bits: Address has the form 0101hjkx where Adr2, Adr1 and Adr0
correspond to h, j and k respectively and x corresponds to the R/W command (0 for Write,
and 1 for Read). Adr[2], Adr[1] and Adr[0] are pulled down to GND through 40 to 125 µA
current source inside TX module.
I3.3 V
LVTTL
D[11:0]+ Module Data Non-inverting Input / Output for channels 11 through 0 I CML
D[11:0]- Module Data Inverting Input/ Output for channels 11 through 0 I CML
NC<6:0> Reserved – Do Not Connect to any electrical potential on Host PCB
GND Signal Common: All module voltages are referenced to this potential unless otherwise
stated. Connect these pins directly to the host board signal ground plane.
IntL Interrupt signal to Host, Asserted Low: An interrupt is generated in response to any Fault
condition, loss of input signal or assertion of any monitor Flag. It may be programmed
through the TWS interface to generate either a pulse or static level with static mode as
default. This output presents a High-Z condition when IntL is de-asserted and requires a
pull-up on the Host board. Pull-up to the Host 3.3 V supply is required.
O3.3 V
LVTTL,
high-Z or
driven to 0
level
ResetL Reset signal to module, Asserted Low: When asserted the optical outputs are disabled,
TWS interface commands are inhibited, and the module returns to default and non-vola-
tile settings. An internal pull-up biases the input High if the input is open.
I3.3 V
LVTTL
SDA TWS interface data signal:
Pull-up with a 2.0 k to 8.0 k resistor to the Host 3.3 V supply is required.
I/O 3.3 V
LVTTL
high-Z or
driven to 0
level
SCL TWS interface clock signal l:
Pull-up with a 2.0 k to 8.0 k resistor to the Host 3.3 V supply is required.
I3.3 V
LVTTL
Vcc25 2.5 V Power supply,
External common connection of pins required – not common internally
Vcc33 3.3 V Power supply,
External common connection of pins required – not common internally
Case
Common
Not accessible in connector. Case common incorporates exposed thermally conductive
surfaces and is electrically isolated from signal common, i.e. GND.
Figure 7. TX / RX Host Board Pattern – Top View
Transmitter / Receiver Module Contact Assignment and Signal Description
Optical Fiber Exit Side
1 2 3 4 5 6 7 8 9
AGND D2+ GND D4+ GND D6+ GND D8+ GND
BGND D2 - GND D4 - GND D6 - GND D8 - GND
CGND GND ADR<2> Vcc33 NC<3> Vcc33 NC<2> GND GND
DD0+ D0 - Vcc33 SDA INTL SDA Vcc33 D10 - D10+
EGND GND ADR<1> SCL NC<4> SCL NC<1> GND GND
FD1+ D1 - Vcc25 RESET INTL NC<6> Vcc25 D11 - D11+
GGND GND ADR<0> Vcc25 NC<5> Vcc25 NC<0> GND GND
HGND D3 - GND D5 - GND D7 - GND D9 - GND
JGND D3+ GND D5+ GND D7+ GND D9+ GND
15 Avago Technologies Confidential – Restricted under NDA
Power Supply Sequence
TX and RX Modules Power Supplies
There is no special requirement in the order of Vcc33 and
Vcc25 power supply up/down sequence for TX or RX mod-
ules. However, it is recommended that
Upon power down, the Vcc33 and Vcc25 shall be within
0 mV to +50 mV. If the residual voltage is larger than
50 mV, it can cause the TX or RX module to fail to start
up.
Host ASIC Power Supplies
It is required that
The maximum delay of power up/down between host
ASIC and TX or RX module shall be shorter than 1 s to
avoid any potential reliability damage to the modules.
It is recommended that: [1]
The host ASIC power supply shall be turned on no later
than TX or RX module power supplies (3.3 V and 2.5 V).
The host ASIC power supply shall be turned off no ear-
lier than module power supplies (3.3 V and 2.5 V).
If this condition cannot be met in the system design, the
following shall be taken into account in the ASIC design.
In the case when the RX module is powered on, host ASIC
is power off, the host ASIC electrical input ESD diodes can
be forward-biased through a 50 resistor to the Vcc25
supply (see Figure 10). The host ASIC ESD diodes shall be
designed to tolerate such forward biasing.
High Speed and Low Speed IOs
The power supply sequence and the ramp rate shall be
designed by the user to meet the absolute maximum
specifications as in “Data Input Voltage – Single Ended”
and “Control Input Voltage”.
It is required that:
Data signal shall NOT be presented at TX high speed
inputs before both Vcc33 and Vcc25 are turned on for
the TX module; and data signal shall be turned off at
TX high speed inputs before both Vcc33 and Vcc25 are
turned off for the TX module.
It is recommended that:
The low speed inputs are pulled down when the TX
and RX Vcc33 or Vcc25 are off.
Recommended Power Supply Filtering
It is recommended to use separate power supply filters for
Vcc33 and Vcc25 as in Figure 8. This filter is similar to other
module specifications, such as SFF-8431 Rev 3.0 section
D17 Figure 56.
Separate power supply filters shall be used for TX and RX
modules.
The host power supply noise level compliance point is at
point X.
The host power supply voltage level compliance point is
at point Y, and host must take into account of the possible
power supply drop due to the LGA interface. Figure 8. Recommended TX and RX Power Supply Filter
Host
Supply
(Vcc33
or
Vcc25)
MicroPOD
LGA
4.7 µH
0.1
µF
0.1
µF
22 µF
0.5
Point X:
Host Vcc
Point Y:
Module Vcc
Note:
1. In the case when host ASIC is turned on and the module power supply is off, the TX high speed input (if DC coupled to ASIC) and TX/RX low speed
IO ESD diodes can be forward-biased by the ASIC. The following design shall take care of the potential latch up or reliability issues:
The TX high speed ESD diodes are designed to tolerate a minimum of 10 mA forward biasing current assuming ASIC is CML driver
The host system or ASIC low speed IO pull-ups shall be sufficient to limit the forward biasing current in the low speed IO ESD diodes.
16 Avago Technologies Confidential – Restricted under NDA
Figure 9. Transmitter Data Input Equivalent Circuit Figure 10. Receiver Data Output Equivalent Circuit
Figure 11. Low Speed IO Equivalent Circuit, INTL Figure 12. Low Speed IO Equivalent Circuit, RESETL
Din p
150 k
VCC 33
Din n
VCC 33
GND
GND
150 k
100 k
GND
100 k
50
50
20 pF
20 pF
150 pF
VCC 25
VCC 25
Dout p
GND
50
Ohms
Dout n
50
Ohms
VCC 25
VCC33
To Pad
Din
1.2V
VCC33
To Pad
Dout
Figure 13. Low Speed IO Equivalent Circuit, ADR<2:0> Figure 14. Low Speed IO Equivalent Circuit, SDA, SCL
To Pad
VCC33
Din
To Pad
Dout
Din
High Voltage
Shunt
J J 5 Fa— \‘ //// _12fl_ / f \ / A \f @—
17 Avago Technologies Confidential – Restricted under NDA
Control Timing Diagrams
Figure 15. Power-Up Sequence Figure 16. ResetL Sequence
Figure 17. Interrupt Sequence
t
PWR INIT
V
CC
33
V
CC
25
V
CC
25 > 2.375 V
TWS Signals
Normal
Operation
Inhibited
TX Outputs
Normal
Operation
Disabled
...
RX Outputs
Normal
Operation
Disabled
t
RSTL OFF
ResetL
t
RSTL PW
t
RSTL ON
TX Outputs Normal
Operation
Disabled
Normal
Operation
t
RSTL ON
...
RX Outputs Normal
Operation
Disabled
Normal
Operation
t
RSTL ON
TWS SignalsNormal
Operation
Inhibited
Normal
Operation
Interrupt Event
SCL
Flag Bit
tFLAG ON
tINTL PW
tINTL ON
IntL
SDA
Normal
Operation
Normal
Operation
tFLAG OFF
tINTL OFF
TWS Read
Transaction
Stop Bit
IntL Pulse Mode
IntL Static Mode
18 Avago Technologies Confidential – Restricted under NDA
Figure 18. Channel Disable Sequence
Figure 19. LOS Squelch Sequence
TWS Write
Transaction
Stop Bit
tDIS ON
SCL
SDA
Disabled
Disabled
tDIS ON
TWS Write
Transaction
Stop Bit
Normal
Operation
tDIS OFF
tDIS OFF
TX Output
RX D+
Output
Normal
Operation
GND
Normal
OperationVcc25
RX D-
Output
Vcc25
GND
Normal
Operation
Disabled
Input LOS Event
TX Output
RX D +
Output
Normal
Operation
Normal
Operation
Squelched
GND
Normal
Operation
Squelched
Flag Bit
IntL
tFLAG ON
tINTL PW
t INTL ON IntL Pulse Mode
IntL Static Mode
tSQ ON
tSQ ON
tSQ OFF
tSQ OFF
Normal
Operation
Vcc25
RX D -
Output
Vcc25
GND
Nickel plated Cu Glass fiber filled heat sinks to plastic lens holder /' FLT ‘\ to support optical module (X2) extract heat from connector 1 Guide pin holes Glass Lens to help align the optical connector (X2) Latch for Optical Connector (X2) Organic substrate \‘ Laser branded text to identify module . Plastic wirebond protector (WBP) Nickel plated Cu leadframe White for TX: black for RX
19 Avago Technologies Confidential – Restricted under NDA
Module Outline
The mechanical outline of the TX and RX module are identical, shown as follows.
To differentiate TX from RX, the color of the TX WBP plastic is chosen to be white and for RX, black.
Figure 20. Module Outline
RX on the left
See Appendix A: Module Mechanical Drawing” for the detailed mechanical dimensions.
TX on the right
_ , _, , «a \, I 4 a bf , ~ 1 ,_ a
20 Avago Technologies Confidential – Restricted under NDA
The TX and RX modules shall be horizontally aligned to the LGA interposer through the module four corner. The LGA
socket design shall be sufficient to guarantee the LGA contacts to the module corresponding substrate pads under the
worst case tolerance. The corner feature of the LGA interposer can be spring loaded, but the horizontal force applied to
the modules shall meet the requirements as in the Mechanical Forces section.
The TX and RX modules shall be pushed down against the LGA interposer on the Cu blocks as shown in Figure 1. The
nominal force is 40 gram per LGA contact, which is 3.240 kg total. The force shall also meet the requirement as in the
Mechanical Forces section. Under such force, the LGA socket shall have a vertical working range of a minimum of 150um.
The TX and RX LGA interface metallurgy over copper pads is electroless nickel, electroless palladium, and immersion
gold (ENEPIG). The plating specification is as follows:
Supplier Ni Plating Thickness (um) Pd Plating Thickness (um) Au Plating Thickness (um)
A 5 to 9 0.08 to 0.15 0.03 to 0.06
K 7 to 13 0.02 to 0.10 0.06 to 0.16
Figure 21. A Module and PRIZM in a Reference LGA Socket
LGA Interface
Host PCB Interface
Host PCB footprint depends on customer LGA solution, which shall meet the dimension and tolerance in order to work
with the LGA interposer and the module substrate outline as in Appendix A: Module Mechanical Drawing
Insertion and Removal Specifications
Parameter Max. Cycles
MicroPOD Insertions into an LGA Socket 20
PRIZM Insertions into a MicroPOD 20
8.41
8.79
R1.04
3.93 ±0.16 1.60 ±0.20
AFTER REFLOW
3.00 ±0.12
FOXCONN SOCKET (PE008127-4840-01H)
21 Avago Technologies Confidential – Restricted under NDA
Mechanical Forces
The following tables specify the maximum forces that can be applied to the TX and RX modules during normal operation
and handling.
Handling Tooling Forces Spec Comments
Module Removal from
Tape and reel package
Pick and Place
Machine
Tensile on Cu rails using vacuum dur-
ing extraction from pocket
<0.5 kgf vacuum head contacts
and loads tops of Cu
sidebars
Optical alignment of
Module over uLGA
socket posts
Pick and Place
Machine
XYZ acceleration (+/-) <0.25m/s2Compliant interfaces on
vacuum head to mini-
mize accelerations
Insertion of Module
into uLGA
Pick and Place
Machine
Vertical (compression) force on Cu
blocks beyond uLGA post retention
features
<0.5 kgf
XY shear (PCN contact to posts with
a displacement of the module while
holding the Cu blocks)
<0.4 kgf
Additional compression on Cu blocks
to uLGA socket stops
<1 kgf
Extraction of Module
from uLGA (rework)
Manual Tweezers
Extraction
Tensile on 1) optical connector and
module interface and 2) TIM0
<0.45 kgf
(4.4 N)
using special tweezers
under a scope
Insertion of optical
connector subassembly
onto module
Manual
Placement
Compression load on FLT plastic with
loads transferred to Cu blocks
<0.45 kgf
Shear forces acting on optical con-
nector and module FLT interface
<0.4 kgf optical connector guide
pin misaligned to FLT
guidepin hole
Fiber connector
assembly handling
pre-Saddle Loading
Manual
Manipulation
Shear forces acting on Cu block TIM0
adhesive
<0.5 kgf Forces transferred from
FO assembly without
loading on Cu blocks to
restrain Module in uLGA
carrier
Fiber connector
assembly handling
post-Saddle Loading
Manual
Manipulation
Shear forces acting on optical con-
nector and module FLT interface
<0.1 kgf Forces transferred
from FO assembly with
loading on Cu blocks to
restrain Module in uLGA
carrier
Fiber connector
assembly handling
post-Saddle Loading
(full compression)
Manual
Manipulation
Shear forces acting on optical con-
nector and module FLT interface
<0.11 kgf
Weight of FO assembly
and overlaying FO stack
Manual
Manipulation
Compressive load on FLT plastics <0.45 kgf
TIM3 Compression Mechanical
Press
Compressive on Cu Sidebars < 12.3 kgf < 24 hours
< 3.6 kgf
(8 lbf)
Subsequent Test/Card
socket loads and system
operation
Imagined Thermal + measurement location for (3 mp heat sink Localion lor heat 5an temperature measurement IS dellned lnthe below llgure. The use ol athermlstor or very lme gauge thermocouple IS recommended The thermocouple or lhcrmlstor should be In dlrecl conlocl wnh 1he module heal-slnk (and should he epnxlad ln place) l '80 0'75
22 Avago Technologies Confidential – Restricted under NDA
Thermal Requirements
The module thermal interfaces are highlighted in blue in Figure 22, which represents two copper blocks as the system
cooling interface. The user shall provide the thermal solution to these interfaces to meet the temperature range as in the
recommended operating conditions.
The case temperature measurement point is highlighted, shown as follows.
The TX and RX modules are not intended for a normal solder reflowing process. Permanent damage can happen to the
modules during the reflow process.
Optical inspection shall be conducted at class 100k or better environment. ESD must be taken care during the operation.
Perform first pass inspection at 30× magnification under a low power scope (e.g., LEICA GZ6E scope with fluorescent
ring white lighting) for optical opening with exposed glass substrate surface.
If the surface is contaminated with foreign debris or particles, use an air gun with clean ionized dry air or nitrogen sup-
ply (pressure at ~ 5kg/cm2) to blow directly into the optical opening (no cotton swabs, no liquid solvents on the optics).
Inspect under scope again. Repeat if necessary.
If the module requires further verification, perform second pass inspection at 80× or higher power. Set focus on the top
surface ONLY of the glass substrate and complete inspection for the exposed area. If there is unacceptable contamina-
tion, the module may be routed back once for cleaning with ionized air.
The surface of the lenses should not be physically touched.
Figure 22. Module Thermal Interface (RX shown)
Optics Inspection and Cleaning
Figure 23. Optical Opening
Optical Area: 3000 x 250 µm center of FLT slot
23 Avago Technologies Confidential – Restricted under NDA
Control Interface and Memory Map
The control interface combines dedicated signal lines for address inputs, Adr[2:0], interrupt output, IntL, and reset input,
ResetL, with two-wire serial, TWS, interface clock, SCL, and data, SDA, signals to provide users rich functionality over an
efficient and easily used interface. The TWS interface is implemented as a slave device and compatible with industry
standard two-wire serial protocol. In general, TWS bus timing and protocols follow the implementation popularized in
Atmel Two-wire Serial EEPROMs. For additional details see, e.g., Atmel AT24C01A. Note the difference in write cycle time
as described later.
Multi-byte writes are supported to allow up to 8 write transactions of up to 16 bytes each.without NACK. If the se-
quence of module actions is important, at least 100 ms wait between each functional change must be used. A func-
tional change is a 1 or 2 byte write affecting one function. For example, if a channel is disabled and then enabled in the
next write, a 100 ms wait period is needed after the disable to ensure it is effective and that the subsequent write or
read is acknowledged. If insufficient wait time is allowed, the write or read following the initial write will receive a NACK
(no-acknowledge). Reads to any location and writes to the page select registers x5i:127 and x6i:127 do not count as
functional changes and do not require any wait time before the next read or write transaction.
The address signals, Adr2, Adr1 and Adr0, provide the ability to program the TWS bus address of the module.
The TX module address has the binary form 0101hjkx, where h, j and k correspond to Adr2, Adr1 and Adr0, respectively
and x corresponds to the Read/Write command bit. Modules will respond to TWS bus addresses in the range of 50h to
5Fh (hereafter 5ih) depending upon the state of Adr2, Adr1 and Adr0.
The RX module address has the binary form 0110hjkx, where h, j and k correspond to Adr2, Adr1 and Adr0, respectively
and x corresponds to the Read/Write command bit. Modules will respond to TWS bus addresses in the range of 60h to
6Fh (hereafter 6ih) depending upon the state of Adr2, Adr1 and Adr0.
An interrupt signal, IntL, is used to alert the host of a loss of input signal (LOS), transmitter fault conditions and/or as-
sertion of any monitor flag. This reduces the need for dedicated status signal lines and polling the status and monitor
registers while maintaining timely alerts to significant events. IntL can be programmed (page 01h byte 225 bit 0) to
either pulse or static mode with static as the default mode.
A dedicated module reset signal, ResetL, is provided in case the TWS interface becomes dysfunctional. When ResetL is
asserted, the outputs are disabled, TWS interface commands are inhibited and the module returns to factory default set-
tings except Non-volatile Read-Write (RW) registers which retain the last write. A module register (memory map except
the non-volatile registers) reset can also be initiated over the TWS interface (TX page 5ih or RX page 6ih byte 91, bit 0). A
TWS reset can be initiated by nine SCL clock cycles with SDA high in each cycle and creating a start condition.
With the TWS interface the user can read a status register (byte 2 for TX page 5ih, RX page 6i) to see if data is available in
the monitor registers, if the module has generated an IntL that has not been cleared and global status reports for loss of
signal and fault conditions.
LOS, TX fault and/or monitor flag registers can be accessed to check the status of individual channels or which channel
may have generated a recent IntL. LOS, TX fault and flag bits remain set (latched) after assertion even in the event the
condition changes and operation resumes until cleared by the read operation of the associated registers or reset by
ResetL or the TWS module reset function.
The user can read the present value of the various monitors. For transmitters and receivers, internal module tempera-
ture and supply voltages are reported. For transmitters, monitors provide for each channel laser bias current and laser
light output power (LOP) information. For receivers, input power (Pave) is monitored for each channel. In addition,
elapsed operating time is reported. All monitor items are two-byte fields and to maintain coherency, the host must ac-
cess these with single two-byte read sequences. For each monitored item, alarm thresholds are established. If an item
moves past a threshold, a flag is set, and, provided the item is not masked, IntL is asserted. The threshold settings are
available in the upper memory page, 01h.
24 Avago Technologies Confidential – Restricted under NDA
The user can select either a pulse or static mode for the interrupt signal IntL and initiate a module register reset. The user
is provided the ability to disable individual channels. For transmitters, equalization levels can be independently set for
individual channels. For receivers, output signal amplitude, de-emphasis levels and rate select can be independently
set for individual channels. In the upper page, 01h, control field the user can invert the truth of the differential inputs
for individual transmitter channel and for the differential outputs of individual receiver channels. In addition, the user
can disable the output squelch function on an individual channel basis for both transmitters and receivers. For transmit-
ters the user can, on an individual channel basis, activate a margin mode that reduces the output optical modulation
amplitude for the channel.
Most non-volatile control registers are located in the upper page 01(h). Other non-volatile functions include the IntL
mode selection bit, input and output polarity flip bits, transmitter equalization control bits, receiver output amplitude
control and receiver output de-emphasis control. Entries into these registers will retain the last write for supply voltage
cycles and for ResetL and module register resets.
Volatile functions include module register reset, channel disable, squelch disable and margin activation.
A mask bit that can be set to prevent assertion of IntL for the individual item exists for every LOS, TX fault and monitor
flag. Mask fields for LOS, TX fault and module monitors are in the lower memory page, 5ih for TX and 6ih for RX, and the
mask field for the channel monitors are in the upper page 01h. Entries in the mask fields are volatile.
Page 00h, based on the Serial ID pages of XFP and QSFP, provides module identity and information regarding the capa-
bilities of the module.
25 Avago Technologies Confidential – Restricted under NDA
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40˚C, Vcc33 = 3.435 V and Vcc25 = 2.625 V.
Parameter Symbol Min Typ Max Units Reference
LVTTL Input Voltage High Threshold Vihttl 2 V Note 1
LVTTL Input Voltage Low Threshold Vilttl 0.8 V Note 1
LVTTL Output Pull-up Current Ioputtl 80 250 µA Pull-up to 3.3 V
LVTTL Output Pull-down Current Ioputtl 80 250 µA Pull-down to 0.0V
Address Assert Time 6.6 100 ms Note 2
Interrupt Assert Time tINTL ON 100 ms Note 3
Interrupt Pulse Width tINTL PW 5 28 50 µs Note 4
Interrupt De-assert Time tINTL OFF 100 ms Note 5
Reset Assert Time tRSTL ON 0.2 100 µs Note 6
Reset De-assert Time tRSTL OFF 350 2000 ms Note 7
Initialization Time TWS Interfaces 2000 ms
Data Ready Time tdata 2000 ms Note 8
Tx Fault Assert Time tTxfault,ON 100 ms Note 9
Flag Assert Time tflag,ON 100 ms Note 10
Mask Assert Time tmask,OFF 100 ms Note 11
Mask Deassert Time tmask,ON 100 ms Note 12
Select Change Time tratesel 100 ms Note 13
TWS Data In Set Up Time tSU:SDA 0.10 µs Note 14
TWS Data In Hold Time tHD:SDA 0 µs Note 15
TWS Clock Low to Data Out Valid tAA 0.10 0.90 µs Note 16
TWS Data Out Hold Time tDH 100 ns Note 17
TWS Data Output Rise Time tr SDA 0.30 µs Measured between
0.8V and 2.0V
TWS Data Output Fall Time tf SDA 0.30 µs
TWS Interface Timing See Atmel Two-Wire Serial EEPROM,
e.g. AT24C01A .
Note difference in Write Cycle Time
TWS Write Cycle Time
(up to 2 sequential bytes)
tWC 100 ms
Serial Interface Clock Holdoff -
“Clock Stretching”
T_clock_hold 500 μs Note 18
Endurance (Write cycles) 50,000 cycles Note 19
Notes:
1. 3.3 V LVTTL compatible control inputs. This includes ADR[2:0] pins.
2. is the module response time from a change in module address, Adr[2:0], to response to TWS communication using the new address.
3. This is the module response time from occurrence of interrupt generating event to IntL assertion, Vout:IntL = Vol. IntL assert time of 100ms
assumes the intL is derived from the logic states of (1) RX LOS status, (2) TX LOS status, or (3) TX FAULT status, or any combination thereof, AND all
other status flags are masked.
4. Pulse or static level can be selected for IntL. Static mode is default. See Memory Map.
5. This is the module response time from clear on read operation, measured from falling SCL edge after stop bit of read transaction, until Vout:IntL =
Voh where IntL is in static mode.
6. Assertion of ResetL activates a complete module reset, i.e. module returns to factory default and non-volatile control settings. While ResetL is Low,
TX and RX outputs are disabled and the module does not respond to the TWS interface.
7. This is the response time from ResetL de-assertion to resumption of operation.
8. Time from power on to Data Not Ready (Byte 2, bit 0) deasserted and Int_L asserted.
9. Time from Tx Fault state to Tx Fault bit set (value = 1b) and Int_L asserted
10. Time from occurrence of condition triggering flag to associated flag bit set (value = 1b) and Int_L asserted. Flag assert/de-assert timings for all
signals assumes the module temperature is stable. Flag assert/de-assert timings may be significantly longer if the module case temperature
changes faster than 4C/min.
11. Time from mask bit set (value = 1b) until associated Int_L assertion is inhibited.
12. Time from mask bit cleared (value = 0b) until associated Int_L operation resumes.
13. Time from change of state of Application or Rate Select bit until transmitter or receiver bandwidth is in conformance with appropriate specification
14. Data In Set Up Time is measured from Vil(max)SDA or Vih(min)SDA to Vil(max)SCL.
15. Data In Hold Time is measured from Vil(max)SCL to Vil(max)SDA or Vih(min)SDA.
16. Clock Low to Data Out Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
17. Data Out Hold Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
18. Maximum time the modules may hold the SCL line low before continuing with a read or write operation.
19. 50K write cycles at 70C. Applies to non-volatile control registers in memory map.
tHD BAT I5U DAT Hm LCM kHD‘STA tSL1 STA ReSTART
26 Avago Technologies Confidential – Restricted under NDA
Management Interface Timing Specification
Field Upgradable Firmware
Boot loader is a programming tool that enables MicroPOD modules to be firmware upgraded in the field over the TWS
interface. Further details on how to use this capability are described in the Appendix.
Figure 24. 2-wire Serial Interface Timing Diagram
Type Lower Memory Page 5|h for TX, 6| [or RX R0 1n|euup1 F1295. LOS‘ Faun, Moni1or In1emallempera|ure as me ule nel RWn Reserved nlanle 1 7 118-126 1 7 » aulL RWv Reserved pper act 5 128-129 1 1 T R0 U \denn‘fiers T U Memo P 128-175 R0 Modu‘eThresno‘ds 01h 1 7 14 15 152-170 171-188 ncnnns Vendor \nlamlanon. Name 5 DUI Vendor \nlamlanon. PN & PN rev Vendor \nlamlanon. Customer Speak: Checksum 241-253 254-255 Vendor Specmc Reserved
27 Avago Technologies Confidential – Restricted under NDA
Memory Map Overview
The memory is structured as a single address, multiple page approach after that in the XFP MSA and adapted by QSFP
MSA for multi-channel transceivers. Figure 25 presents an overview of the memory structure showing a lower page (5ih
for TX and 6i for RX) and two upper pages (00h and 01h). As with XFP and QSFP, time sensitive, dynamic and/or high
interest information are contained in the base, i.e. lower, page. Here the upper page 00h contains the serial id informa-
tion, again following the style of XFP and QSFP. The 01h upper table contains static threshold information, configuration
controls and flag masks.
Figure 25. Two-Wire Serial Address 5ih (TX) or 6ih (RX) Page Structure
Unless otherwise stated all reserved bytes are coded 00h and all reserved bits are coded 0b.
Non-volatile read-write bits are labeled RWn and volatile read-write bits are labeled RWv.
Byte Type Lower Memory Page 5ih for TX, 6i for RX
0 RO Identifier RO Read Only
1-2 RO Status RWv Read/Write volatile
3-27 RO Interrupt Flags: LOS, Fault, Monitor RWn Read/Write non-volatile
28-39 RO Module Monitors (internal temperature, Vcc33, Vcc25)
40-87 RO Channel Monitors(TX bias, TX Output Power, RX Input Power)
88-89 RO Elapsed Operating Time
90 RWn Reserved
91-105 RWvVolatile Controls (Reset, CH Disable, CH Squelch Disable, TX
Margin Enable, RX Rate Select)
106-117RWv Masks: LOS, Fault, Module Flags
118-126 RWv Reserved
127 RWv Upper Page Select Byte
Byte Type Upper Memory Page 00h Byte Type Upper Memory Page 01h
128-129 RO Identifiers
128-175 RO Module Thresholds
130 RO Description: Power Supplies
176-223 RO Channel Thresholds
131 RO Description: Max Case Temp 224 RO Checksum
132-133 RO Description: Min/Max Signal Rate
225-243RWnNon-volatile Controls (IntL Mode, CH Polarity, TX
Equalization, RX De-emphasis & Output Amplitude)
134-137 RO Description: Wavelength
244-255RWv Masks: Channel Monitor Flags
138-143 RO Description: Supported Functions
144-151 RO Reserved
152-170 RO Vendor Information: Name & OUI
171-188 RO Vendor Information: PN & PN rev
189-204 RO Vendor Information: SN
205-212 RO Vendor Information: Date Code
213-222 RO Vendor Information: Customer Specifc
223 RO Checksum
224-239 RWv Reserved
240 RO Reserved
241-253 RO Vendor Specific
254-255 RO Reserved
28 Avago Technologies Confidential – Restricted under NDA
Digital Monitoring Interface
Through TWS interface, the host can fetch the monitoring data as summarized in the previous section.
The following table summarizes the function and the specifications.
Digital Monitoring Specifications
Monitor
Parameter Unit
Tolerance DMI Range* Alarm Setting
Commentmin max min max min max
Vcc33 volt -0.1 +0.1 3.035 3.565 3.035 3.565 Test point at module MEG-Array connector
under module low power condition
Vcc25 volt -0.1 +0.1 2.275 2.725 2.275 2.725
Temperature C -5 +5 -5 95 -5 95 Internal IC temperature at module low
power condition
TX Bias
current
mA -1 +1 0 11 2 10 Note 1
TX Light
Output Power
dB/dBm - 3 +3 -9 +2.4 -9 +3 at TP2
RX Light Input
Power
dB/dBm - 3 +3 -10 +2.4 -10 +3 at TP3
* Within DMI range, the tolerance is guaranteed. The modules still reports data if the operating condition is out of the DMI range, but the tolerance
is not guaranteed.
Note
1. TX bias DMI report accuracy not guaranteed when TX squelch is disabled, and LOS is asserted, i.e. no valid electrical inputs into TX.
29 Avago Technologies Confidential – Restricted under NDA
TX Memory Map 5ih Lower Page
Details of the base or lower page of the memory map for a transmitter follow.
Address
Type Field Name/DescriptionByte Bit
0 all RO Type Identifier: Coded 00h for unspecified
1 all RO Reserved Status: Coded 00h
2 7-4 RO Reserved: Coded 0000b
2 3 RO Fault Status: Coded 1 when a Fault flag (bytes 11 and 12 of this page) is asserted for any channel,
else 0. Clears when Fault flags are cleared.
2 2 RO LOS Status: Coded 1 when a LOS flag (bytes 9 and 10 of this page) is asserted for any channel, else 0.
Clears when LOS flags are cleared.
2 1 RO IntL Status: Coded 1 for asserted IntL. Clears to 0 when all flags including LOS and Fault are cleared.
2 0 RO Data Not Ready: Coded 1 until data is available in monitor registers. Coded 0 in normal operation.
3 - 8 all RO Reserved Flags: Coded 00h
9 7-4 RO Reserved: Coded 0000b
9 3 RO LOS Latched TX Channel 11: Coded 1 when asserted, Latched, Clears on Read.
9 2 RO LOS Latched TX Channel 10: Coded 1 when asserted, Latched, Clears on Read.
9 1 RO LOS Latched TX Channel 9: Coded 1 when asserted, Latched, Clears on Read.
9 0 RO LOS Latched TX Channel 8: Coded 1 when asserted, Latched, Clears on Read.
10 7 RO LOS Latched TX Channel 7: Coded 1 when asserted, Latched, Clears on Read.
10 6 RO LOS Latched TX Channel 6: Coded 1 when asserted, Latched, Clears on Read.
10 5 RO LOS Latched TX Channel 5: Coded 1 when asserted, Latched, Clears on Read.
10 4 RO LOS Latched TX Channel 4: Coded 1 when asserted, Latched, Clears on Read.
10 3 RO LOS Latched TX Channel 3: Coded 1 when asserted, Latched, Clears on Read.
10 2 RO LOS Latched TX Channel 2: Coded 1 when asserted, Latched, Clears on Read.
10 1 RO LOS Latched TX Channel 1: Coded 1 when asserted, Latched, Clears on Read.
10 0 RO LOS Latched TX Channel 0: Coded 1 when asserted, Latched, Clears on Read.
11 7-4 RO Reserved: Coded 0000b
11 3 RO Fault Latched TX Channel 11: Coded 1 when asserted, Latched, Clears on Read.
11 2 RO Fault Latched TX Channel 10: Coded 1 when asserted, Latched, Clears on Read.
11 1 RO Fault Latched TX Channel 9: Coded 1 when asserted, Latched, Clears on Read.
11 0 RO Fault Latched TX Channel 8: Coded 1 when asserted, Latched, Clears on Read.
12 7 RO Fault Latched TX Channel 7: Coded 1 when asserted, Latched, Clears on Read.
12 6 RO Fault Latched TX Channel 6: Coded 1 when asserted, Latched, Clears on Read.
12 5 RO Fault Latched TX Channel 5: Coded 1 when asserted, Latched, Clears on Read.
12 4 RO Fault Latched TX Channel 4: Coded 1 when asserted, Latched, Clears on Read.
12 3 RO Fault Latched TX Channel 2: Coded 1 when asserted, Latched, Clears on Read.
12 2 RO Fault Latched TX Channel 2: Coded 1 when asserted, Latched, Clears on Read.
12 1 RO Fault Latched TX Channel 1: Coded 1 when asserted, Latched, Clears on Read.
12 0 RO Fault Latched TX Channel 0: Coded 1 when asserted, Latched, Clears on Read.
13 7 RO High Internal Temperature Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
13 6 RO Low Internal Temperature Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
13 5-0 RO Reserved
14 7 RO High Internal 3.3 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 6 RO Low Internal 3.3 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 5-4 RO Reserved
14 3 RO High Internal 2.5 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 2 RO Low Internal 2.5 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
30 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
14 1-0 RO Reserved
15 all RO Reserved: Coded 00h
16 7 RO High TX Bias Current Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
16 6 RO Low TX Bias Current Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
16 5-4 RO Reserved
16 3 RO High TX Bias Current Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
16 2 RO Low TX Bias Current Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
16 1-0 RO Reserved
17 7 RO High TX Bias Current Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
17 6 RO Low TX Bias Current Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
17 5-4 RO Reserved
17 3 RO High TX Bias Current Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
17 2 RO Low TX Bias Current Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
17 1-0 RO Reserved
18 7 RO High TX Bias Current Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
18 6 RO Low TX Bias Current Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
18 5-4 RO Reserved
18 3 RO High TX Bias Current Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
18 2 RO Low TX Bias Current Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
18 1-0 RO Reserved
19 7 RO High TX Bias Current Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
19 6 RO Low TX Bias Current Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
19 5-4 RO Reserved
19 3 RO High TX Bias Current Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
19 2 RO Low TX Bias Current Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
19 1-0 RO Reserved
20 7 RO High TX Bias Current Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
20 6 RO Low TX Bias Current Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
20 5-4 RO Reserved
20 3 RO High TX Bias Current Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
20 2 RO Low TX Bias Current Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
20 1-0 RO Reserved
21 7 RO High TX Bias Current Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
21 6 RO Low TX Bias Current Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
21 5-4 RO Reserved
21 3 RO High TX Bias Current Alarm Latched Channel 0: Coded 1 when asserted, Latched, Clears on Read.
21 2 RO Low TX Bias Current Alarm Latched Channel 0: Coded 1 when asserted, Latched, Clears on Read.
21 1-0 RO Reserved
22 7 RO High TX Power Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
22 6 RO Low TX Power Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
22 5-4 RO Reserved
22 3 RO High TX Power Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
22 2 RO Low TX Power Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
22 1-0 RO Reserved
23 7 RO High TX Power Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
23 6 RO Low TX Power Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
23 5-4 RO Reserved
31 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
23 3 RO High TX Power Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
23 2 RO Low TX Power Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
23 1-0 RO Reserved
24 7 RO High TX Power Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
24 6 RO Low TX Power Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
24 5-4 RO Reserved
24 3 RO High TX Power Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
24 2 RO Low TX Power Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
24 1-0 RO Reserved
25 7 RO High TX Power Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
25 6 RO Low TX Power Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
25 5-4 RO Reserved
25 3 RO High TX Power Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
25 2 RO Low TX Power Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
25 1-0 RO Reserved
26 7 RO High TX Power Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
26 6 RO Low TX Power Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
26 5-4 RO Reserved
26 3 RO High TX Power Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
26 2 RO Low TX Power Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
26 1-0 RO Reserved
27 7 RO High TX Power Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
27 6 RO Low TX Power Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
27 5-4 RO Reserved
27 3 RO High TX Power Alarm Latched Channel 0: Coded 1 when asserted, Latched, Clears on Read.
27 2 RO Low TX Power Alarm Latched Channel 0: Coded 1 when asserted, Latched, Clears on Read.
27 1-0 RO Reserved
28 all RO Internal Temperature Monitor MSB: Integer part coded in signed 2’s complement. Tolerance is ± 3
°C.
29 all RO Internal Temperature Monitor LSB: Fractional part in units of 1˚/256 coded in binary.
30-31 all RO Reserved: Coded 00h
32-33 all RO Internal 3.3 Vcc Monitor: Voltage in 100 µV units coded as 16 bit unsigned integer, Byte 32 is MSB.
Tolerance is ± 0.1V.
34-35 all RO Internal 2.5 Vcc Monitor: Voltage in 100 µV units coded as 16 bit unsigned integer, Byte 34 is MSB.
Tolerance is ± 0.1V.
36-39 all RO Reserved Monitor: Coded 00h
40-41 all RO TX Bias Current Monitor Channel 11: Bias current in 2 µA units coded as 16 bit unsigned integer,
Byte 40 is MSB. Tolerance is ± 1 mA.
42-43 all RO TX Bias Current Monitor Channel 10: Bias current in 2 µA units coded as 16 bit unsigned integer,
Byte 42 is MSB. Tolerance is ± 1 mA
44-45 all RO TX Bias Current Monitor Channel 9: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
44 is MSB. Tolerance is ± 1 mA
46-47 all RO TX Bias Current Monitor Channel 8: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
46 is MSB. Tolerance is ± 1 mA
48-49 all RO TX Bias Current Monitor Channel 7: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
48 is MSB. Tolerance is ± 1 mA
50-51 all RO TX Bias Current Monitor Channel 6: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
50 is MSB. Tolerance is ± 1 mA
32 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
52-53 all RO TX Bias Current Monitor Channel 5: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
52 is MSB. Tolerance is ± 1 mA
54-55 all RO TX Bias Current Monitor Channel 4: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
54 is MSB. Tolerance is ± 1 mA
56-57 all RO TX Bias Current Monitor Channel 3: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
56 is MSB. Tolerance is ± 1 mA
58-59 all RO TX Bias Current Monitor Channel 2: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
58 is MSB. Tolerance is ± 1 mA
60-61 all RO TX Bias Current Monitor Channel 1: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
60 is MSB. Tolerance is ± 1 mA
62-63 all RO TX Bias Current Monitor Channel 0: Bias current in 2 µA units coded as 16 bit unsigned integer, Byte
62 is MSB. Tolerance is ± 1 mA
64-65 all RO TX Light Output Monitor Channel 11: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 64 is MSB. Tolerance is ± 3 dB.
66-67 all RO TX Light Output Monitor Channel 10: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 66 is MSB. Tolerance is ± 3 dB.
68-69 all RO TX Light Output Monitor Channel 9: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 68 is MSB. Tolerance is ± 3 dB
70-71 all RO TX Light Output Monitor Channel 8: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 70 is MSB. Tolerance is ± 3 dB.
72-73 all RO TX Light Output Monitor Channel 7: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 72 is MSB. Tolerance is ± 3 dB.
74-75 all RO TX Light Output Monitor Channel 6: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 74 is MSB. Tolerance is ± 3 dB.
76-77 all RO TX Light Output Monitor Channel 5: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 76 is MSB. Tolerance is ± 3 dB.
78-79 all RO TX Light Output Monitor Channel 4: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 78 is MSB. Tolerance is ± 3 dB.
80-81 all RO TX Light Output Monitor Channel 3: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 80 is MSB. Tolerance is ± 3 dB.
82-83 all RO TX Light Output Monitor Channel 2: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 82 is MSB. Tolerance is ± 3 dB.
84-85 all RO TX Light Output Monitor Channel 1: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 84 is MSB. Tolerance is ± 3 dB.
86-87 all RO TX Light Output Monitor Channel 0: Optical power in 0.1 µW units coded as 16 bit unsigned inte-
ger, Byte 86 is MSB. Tolerance is ± 3 dB
88-89 all RO Elapsed (Power-on) Operating Time: Elapsed time in 2 hour units coded as 16 bit unsigned integer,
Byte 88 is MSB, Tolerance is ± 10%
90 all RWn Reserved Control: Coded 00h
91 7-1 RWv Reserved: Coded 0000000b
91 0 RWv Transmitter Reset: Writing 1 return all registers except non-volatile RW to factory default values.
Reads 0 after operation.
92 7-4 RWv Reserved: Coded 0000b
92 3 RWv TX Channel 11 Disable: Writing 1 deactivates the optical output, Default is 0.
92 2 RWv TX Channel 10 Disable: Writing 1 deactivates the optical output, Default is 0.
92 1 RWv TX Channel 9 Disable: Writing 1 deactivates the optical output, Default is 0.
92 0 RWv TX Channel 8 Disable: Writing 1 deactivates the optical output, Default is 0.
93 7 RWv TX Channel 7 Disable: Writing 1 deactivates the optical output, Default is 0.
93 6 RWv TX Channel 6 Disable: Writing 1 deactivates the optical output, Default is 0.
93 5 RWv TX Channel 5 Disable: Writing 1 deactivates the optical output, Default is 0.
33 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
93 4 RWv TX Channel 4 Disable: Writing 1 deactivates the optical output, Default is 0.
93 3 RWv TX Channel 3 Disable: Writing 1 deactivates the optical output, Default is 0.
93 2 RWv TX Channel 2 Disable: Writing 1 deactivates the optical output, Default is 0.
93 1 RWv TX Channel 1 Disable: Writing 1 deactivates the optical output, Default is 0.
93 0 RWv TX Channel 0 Disable: Writing 1 deactivates the optical output, Default is 0.
94 7-4 RWv Reserved: Coded 0000b
94 3 RWv Squelch Disable Channel 11: Writing 1 inhibits squelch for the channel, Default is 0.
94 2 RWv Squelch Disable Channel 10: Writing 1 inhibits squelch for the channel, Default is 0.
94 1 RWv Squelch Disable Channel 9: Writing 1 inhibits squelch for the channel, Default is 0.
94 0 RWv Squelch Disable Channel 8: Writing 1 inhibits squelch for the channel, Default is 0.
95 7 RWv Squelch Disable Channel 7: Writing 1 inhibits squelch for the channel, Default is 0.
95 6 RWv Squelch Disable Channel 6: Writing 1 inhibits squelch for the channel, Default is 0.
95 5 RWv Squelch Disable Channel 5: Writing 1 inhibits squelch for the channel, Default is 0.
95 4 RWv Squelch Disable Channel 4: Writing 1 inhibits squelch for the channel, Default is 0.
95 3 RWv Squelch Disable Channel 3: Writing 1 inhibits squelch for the channel, Default is 0.
95 2 RWv Squelch Disable Channel 2: Writing 1 inhibits squelch for the channel, Default is 0.
95 1 RWv Squelch Disable Channel 1: Writing 1 inhibits squelch for the channel, Default is 0.
95 0 RWv Squelch Disable Channel 0: Writing 1 inhibits squelch for the channel, Default is 0.
96-98 all RWv Reserved: Coded 00h
99 7-4 RWv Reserved: Coded 0000b
99 3 RWv Margin Activation Channel 11: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
99 2 RWv Margin Activation Channel 10: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
99 1 RWv Margin Activation Channel 9: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 0 RWv Margin Activation Channel 8: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 7 RWv Margin Activation Channel 7: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 6 RWv Margin Activation Channel 6: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 5 RWv Margin Activation Channel 5: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 4 RWv Margin Activation Channel 4: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 3 RWv Margin Activation Channel 3: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 2 RWv Margin Activation Channel 2: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 1 RWv Margin Activation Channel 1: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
100 0 RWv Margin Activation Channel 0: Writing 1 places channel into Margin mode (Reduces OMA by 1 dB),
Default is 0.
101 7–0 RWv Reserved: Coded 00h
102-105 all RWv Reserved Controls: Coded 00h
106-111 all RWv Reserved Masks: Coded 00h
34 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
112 7-4 RWv Reserved: Coded 0000b
112 3 RWv Mask LOS TX Channel 11: Writing 1 Prevents IntL generation, Default = 0
112 2 RWv Mask LOS TX Channel 10: Writing 1 Prevents IntL generation, Default = 0
112 1 RWv Mask LOS TX Channel 9: Writing 1 Prevents IntL generation, Default = 0
112 0 RWv Mask LOS TX Channel 8: Writing 1 Prevents IntL generation, Default = 0
113 7 RWv Mask LOS TX Channel 7: Writing 1 Prevents IntL generation, Default = 0
113 6 RWv Mask LOS TX Channel 6: Writing 1 Prevents IntL generation, Default = 0
113 5 RWv Mask LOS TX Channel 5: Writing 1 Prevents IntL generation, Default = 0
113 4 RWv Mask LOS TX Channel 4: Writing 1 Prevents IntL generation, Default = 0
113 3 RWv Mask LOS TX Channel 3: Writing 1 Prevents IntL generation, Default = 0
113 2 RWv Mask LOS TX Channel 2: Writing 1 Prevents IntL generation, Default = 0
113 1 RWv Mask LOS TX Channel 1: Writing 1 Prevents IntL generation, Default = 0
113 0 RWv Mask LOS TX Channel 0: Writing 1 Prevents IntL generation, Default = 0
114 7-4 RWv Reserved: Coded 0000b
114 3 RWv Mask Fault TX Channel 11: Writing 1 Prevents IntL generation, Default = 0
114 2 RWv Mask Fault TX Channel 10: Writing 1 Prevents IntL generation, Default = 0
114 1 RWv Mask Fault TX Channel 9: Writing 1 Prevents IntL generation, Default = 0
114 0 RWv Mask Fault TX Channel 8: Writing 1 Prevents IntL generation, Default = 0
115 7 RWv Mask Fault TX Channel 7: Writing 1 Prevents IntL generation, Default = 0
115 6 RWv Mask Fault TX Channel 6: Writing 1 Prevents IntL generation, Default = 0
115 5 RWv Mask Fault TX Channel 5: Writing 1 Prevents IntL generation, Default = 0
115 4 RWv Mask Fault TX Channel 4: Writing 1 Prevents IntL generation, Default = 0
115 3 RWv Mask Fault TX Channel 3: Writing 1 Prevents IntL generation, Default = 0
115 2 RWv Mask Fault TX Channel 2: Writing 1 Prevents IntL generation, Default = 0
115 1 RWv Mask Fault TX Channel 1: Writing 1 Prevents IntL generation, Default = 0
115 0 RWv Mask Fault TX Channel 0: Writing 1 Prevents IntL generation, Default = 0
116 7 RWv Mask High Internal Temperature Alarm: Writing 1 Prevents IntL generation, Default = 0
116 6 RWv Mask Low Internal Temperature Alarm: Writing 1 Prevents IntL generation, Default = 0
116 5-0 RWv Reserved
117 7 RWv Mask High Internal 3.3 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 6 RWv Mask Low Internal 3.3 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 5-4 RWv Reserved
117 3 RWv Mask High Internal 2.5 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 2 RWv Mask Low Internal 2.5 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 1-0 RWv Reserved
118-122 all RWn Reserved
123-126 all RWv Reserved: Coded 00h
127 all RWv Page Select Byte
35 Avago Technologies Confidential – Restricted under NDA
TX Memory Map 00h Upper Page
Transmitter serial ID page 00h entries and a description of the registers follow.
Address Contents
Type Field Name/DescriptionByte Bit Code
128 all 00h RO Type Identifier: Coded 00h for unspecified. See SFF-8472 for reference
129 all 01000010b RO Module Description: Coded for < 2.0 W max, Controlled Launch
130 all 11000000b RO Required Power Supplies: Coded for 3.3 V and 2.5 V supplies
131 all 01010101b RO Max Short-term Operating Case Temperature in °C: Coded for 85 °C
132 all 00001100b RO Min Bit Rate in 100 Mb/s units: Coded for 1250 Mb/s
133 all 01100111b RO Max Bit Rate in 100 Mb/s units: Coded for 10312 Mb/s
134-135 all 42h 04h RO Nominal Laser Wavelength (Wavelength in nm = value / 20): Coded for 845 nm
136-137 all 0Bh BBh RO Wavelength deviation from nominal (Wavelength tolerance in nm = ± value / 200):
Coded for 15 nm
138 all 11001000b RO Supported Flags/Actions: Coded for TX Fault, TX LOS, Output Squelch for LOS,
Alarm Flags
139 all 11000101b RO Supported Monitors: Coded for TX Bias, TX LOP, Internal Temp, Elapsed Time
140 all 01100000b RO Supported Monitors: Coded for 3.3 V, 2.5 V
141 all 10100010b RO Supported Controls: Coded for Ch Disable, Squelch Disable, Input Equalization
142 all 00001011b RO Supported Controls: Coded for Margin Mode, Ch Polarity Flip, Module Addressing
143 all 00h RO Supported Functions
144-151 all 00h RO Reserved
152-167 all 41h 56h 41h
47h 4Fh 20h
20h x10
RO Vendor Name in ASCII: Coded AVAGO” for Avago Technologies, Spaces (20h) for
unused characters. Left justified.
168-170 all 00h 17h 6Ah RO Vendor OUI (IEEE ID): Coded “00h 17h 6Ah” for Avago Technologies
171-186 all 41h 46h RO Vendor Part Number in ASCII: AFBR-77D13SZ . Left justified with spaces (20h) for
unused bytes.
42h 52h
2Dh 37h
37h 44h
31h 53h
53h 5Ah
20h 20h
187-188 all 20h 20h RO Vendor Revision Number in ASCII: Coded with spaces (20h)
189-204 all RO Vendor Serial Number (ASCII): Varies by unit. Left justified with space (20h) for
unused bytes
205-212 all RO Vendor Date Code YYYYMMDD (ASCII)
213-222 all RO Customer Specific Area.
223 all RO Check sum addresses 128 through 222
224-255 all RO Vendor Specific
36 Avago Technologies Confidential – Restricted under NDA
TX Memory Map 01h Upper Page
Details of transmitter upper page 01h follow.
Address
Type Field Name/DescriptionByte Bit
128 all RO Internal Temperature High Alarm Threshold MSB: Integer part coded in signed 2’s complement
129 all RO Internal Temperature High Alarm Threshold LSB: Fractional part in units of 1˚/256 coded in
binary.
130 all RO Internal Temperature Low Alarm Threshold MSB: Integer part coded in signed 2’s complement
131 all RO Internal Temperature Low Alarm Threshold LSB: Fractional part in units of 1˚/256 coded in
binary.
132-143 all RO Reserved: Coded 00h
144-145 all RO Internal 3.3 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer,
low address is MSB.
146-147 all RO Internal 3.3 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer,
low address is MSB.
148-151 all RO Reserved
152-153 all RO Internal 2.5 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer,
low address is MSB.
154-155 all RO Internal 2.5 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer,
low address is MSB.
156-159 all RO Reserved
160-175 all RO Thresholds Reserved: Coded 00h
176-177 all RO TX Bias Current All Channels High Alarm Threshold: Current in 2 µA units coded as 16 bit un-
signed integer, low address is MSB.
178-179 all RO TX Bias Current All Channels Low Alarm Threshold: Current in 2 µA units coded as 16 bit un-
signed integer, low address is MSB.
180-183 all RO Reserved
184-185 all RO TX Optical Power All Channels High Alarm Threshold: Optical power in 0.1 µW units coded as 16
bit unsigned integer, low address is MSB.
186-187 all RO TX Optical Power All Channels Low Alarm Threshold: Optical power in 0.1 µW units coded as 16
bit unsigned integer, low address is MSB.
188-223 all RO Thresholds Reserved: Coded 00h
224 all RO Check sum: Low order 8 bits of the sum of all bytes from 128 through 223 inclusive
225 7-1 RWn Reserved: Coded 0000000b
225 0 RWn IntL Pulse/Static Option: Writing 1 sets IntL to Static mode, Default is 1 for Static mode
226 7-4 RWn Reserved: Coded 0000b
226 3 RWn Input Polarity Flip Channel 11: Writing 1 inverts truth of the differential input pair, Default is 0.
226 2 RWn Input Polarity Flip Channel 10: Writing 1 inverts truth of the differential input pair, Default is 0.
226 1 RWn Input Polarity Flip Channel 9: Writing 1 inverts truth of the differential input pair, Default is 0.
226 0 RWn Input Polarity Flip Channel 8: Writing 1 inverts truth of the differential input pair, Default is 0.
227 7 RWn Input Polarity Flip Channel 7: Writing 1 inverts truth of the differential input pair, Default is 0.
227 6 RWn Input Polarity Flip Channel 6: Writing 1 inverts truth of the differential input pair, Default is 0.
227 5 RWn Input Polarity Flip Channel 5: Writing 1 inverts truth of the differential input pair, Default is 0.
227 4 RWn Input Polarity Flip Channel 4: Writing 1 inverts truth of the differential input pair, Default is 0.
227 3 RWn Input Polarity Flip Channel 3: Writing 1 inverts truth of the differential input pair, Default is 0.
227 2 RWn Input Polarity Flip Channel 2: Writing 1 inverts truth of the differential input pair, Default is 0.
227 1 RWn Input Polarity Flip Channel 1: Writing 1 inverts truth of the differential input pair, Default is 0.
227 0 RWn Input Polarity Flip Channel 0: Writing 1 inverts truth of the differential input pair, Default is 0.
37 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
228 7-4 RWn TX Input Equalization Control Channel 11: See Code Description on page 39. Default = 0010b
228 3-0 RWn TX Input Equalization Control Channel 10: See Code Description on page 39. Default = 0010b
229 7-4 RWn TX Input Equalization Control Channel 9: See Code Description on page 39. Default = 0010b
229 3-0 RWn TX Input Equalization Control Channel 8: See Code Description on page 39. Default = 0010b
230 7-4 RWn TX Input Equalization Control Channel 7: See Code Description on page 39. Default = 0010b
230 3-0 RWn TX Input Equalization Control Channel 6: See Code Description on page 39. Default = 0010b
231 7-4 RWn TX Input Equalization Control Channel 5: See Code Description on page 39. Default = 0010b
231 3-0 RWn TX Input Equalization Control Channel 4: See Code Description on page 39. Default = 0010b
232 7-4 RWn TX Input Equalization Control Channel 3: See Code Description on page 39. Default = 0010b
232 3-0 RWn TX Input Equalization Control Channel 2: See Code Description on page 39. Default = 0010b
233 7-4 RWn TX Input Equalization Control Channel 1: See Code Description on page 39. Default = 0010b
233 3-0 RWn TX Input Equalization Control Channel 0: See Code Description on page 39. Default = 0010b
234-243 all RWn Reserved Controls: Coded 00h
244 7 RWv Mask High TX Bias Current Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
244 6 RWv Mask Low TX Bias Current Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
244 5-4 RWv Reserved
244 3 RWv Mask High TX Bias Current Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
244 2 RWv Mask Low TX Bias Current Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
244 1-0 RWv Reserved
245 7 RWv Mask High TX Bias Current Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
245 6 RWv Mask Low TX Bias Current Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
245 5-4 RWv Reserved
245 3 RWv Mask High TX Bias Current Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
245 2 RWv Mask Low TX Bias Current Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
245 1-0 RWv Reserved
246 7 RWv Mask High TX Bias Current Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
246 6 RWv Mask Low TX Bias Current Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
246 5-4 RWv Reserved
246 3 RWv Mask High TX Bias Current Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
246 2 RWv Mask Low TX Bias Current Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
246 1-0 RWv Reserved
247 7 RWv Mask High TX Bias Current Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
247 6 RWv Mask Low TX Bias Current Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
247 5-4 RWv Reserved
247 3 RWv Mask High TX Bias Current Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
247 2 RWv Mask Low TX Bias Current Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
247 1-0 RWv Reserved
248 7 RWv Mask High TX Bias Current Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
248 6 RWv Mask Low TX Bias Current Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
248 5-4 RWv Reserved
248 3 RWv Mask High TX Bias Current Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
248 2 RWv Mask Low TX Bias Current Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
248 1-0 RWv Reserved
38 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
249 7 RWv Mask High TX Bias Current Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
249 6 RWv Mask Low TX Bias Current Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
249 5-4 RWv Reserved
249 3 RWv Mask High TX Bias Current Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
249 2 RWv Mask Low TX Bias Current Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
249 1-0 RWv Reserved
250 7 RWv Mask High TX Power Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
250 6 RWv Mask Low TX Power Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
250 5-4 RWv Reserved
250 3 RWv Mask High TX Power Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
250 2 RWv Mask Low TX Power Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
250 1-0 RWv Reserved
251 7 RWv Mask High TX Power Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
251 6 RWv Mask Low TX Power Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
251 5-4 RWv Reserved
251 3 RWv Mask High TX Power Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
251 2 RWv Mask Low TX Power Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
251 1-0 RWv Reserved
252 7 RWv Mask High TX Power Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
252 6 RWv Mask Low TX Power Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
252 5-4 RWv Reserved
252 3 RWv Mask High TX Power Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
252 2 RWv Mask Low TX Power Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
252 1-0 RWv Reserved
253 7 RWv Mask High TX Power Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
253 6 RWv Mask Low TX Power Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
253 5-4 RWv Reserved
253 3 RWv Mask High TX Power Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
253 2 RWv Mask Low TX Power Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
253 1-0 RWv Reserved
254 7 RWv Mask High TX Power Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
254 6 RWv Mask Low TX Power Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
254 5-4 RWv Reserved
254 3 RWv Mask High TX Power Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
254 2 RWv Mask Low TX Power Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
254 1-0 RWv Reserved
255 7 RWv Mask High TX Power Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
255 6 RWv Mask Low TX Power Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
255 5-4 RWv Reserved
255 3 RWv Mask High TX Power Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
255 2 RWv Mask Low TX Power Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
255 1-0 RWv Reserved
% \.
39 Avago Technologies Confidential – Restricted under NDA
Transmitter Input Equalization Control Code Description
Control registers 228 through 233 permit input equalization control. Four bit code blocks (either bits 7 through 4 or 3
through 0 where bit 7 or 3 is the MSB) are assigned to each channel. Codes 1xxx are reserved. Code 0111 calls for full
scale equalization, code 0000 calls for no equalization, and intermediate code values provide intermediate levels of
equalization.
The following table summarizes the normalized equalization setting effects (TX IC equalizer only)
EQ Setting "111" "110" "101" "100" "011" "010" "001" "000"
Peak vs. Midband dB 16.2 13.5 11.0 8.3 5.8 3.5 1.8 0.2
Peak dB 6.0 5.3 4.6 3.8 2.9 1.9 1.1 0.2
Midband dB -10.2 -8.2 -6.4 -4.5 -2.9 -1.6 -0.7 0.0
Figure 26. Normalized Equalization Transfer Function vs. Settings
0
2
4
6
8
10
12
14
16
18
0
EQ Setting
Peak vs. mid Band (dB)
-15
-10
-5
0
5
10
1.E+04
Frequency (Hz)
Normalized Equalizer Transfer Function (dB)
1.E+05 1.E+111.E+101.E+091.E+081.E+071.E+06 1 765432
"111"
"110"
"101"
"100"
"011"
"010"
"001"
"000"
40 Avago Technologies Confidential – Restricted under NDA
RX Memory Map 6ih Lower Page
Details of the base or lower page of the memory map for a receiver are as follows.
Address
Type Field Name/DescriptionByte Bit
0 all RO Type Identifier: Coded 00h for unspecified
1 all RO Reserved Status: Coded 00h
2 7-3 RO Reserved: Coded 000000b
2 2 RO LOS Status: Coded 1 when a LOS flag (bytes 9 and 10 of this page) is asserted for any channel, else 0.
Clears when LOS flags are cleared.
2 1 RO IntL Status: Coded 1 for asserted IntL. Clears to 0 when all flags including LOS are cleared.
2 0 RO Data Not Ready: Coded 1 until data is available in monitor registers. Coded 0 in normal operation.
3 - 8 all RO Reserved Flags: Coded 00h
9 7-4 RO Reserved: Coded 0000b
9 3 RO LOS Latched RX Channel 11: Coded 1 when asserted, Latched, Clears on Read.
9 2 RO LOS Latched RX Channel 10: Coded 1 when asserted, Latched, Clears on Read.
9 1 RO LOS Latched RX Channel 9: Coded 1 when asserted, Latched, Clears on Read.
9 0 RO LOS Latched RX Channel 8: Coded 1 when asserted, Latched, Clears on Read.
10 7 RO LOS Latched RX Channel 7: Coded 1 when asserted, Latched, Clears on Read.
10 6 RO LOS Latched RX Channel 6: Coded 1 when asserted, Latched, Clears on Read.
10 5 RO LOS Latched RX Channel 5: Coded 1 when asserted, Latched, Clears on Read.
10 4 RO LOS Latched RX Channel 4: Coded 1 when asserted, Latched, Clears on Read.
10 3 RO LOS Latched RX Channel 3: Coded 1 when asserted, Latched, Clears on Read.
10 2 RO LOS Latched RX Channel 2: Coded 1 when asserted, Latched, Clears on Read.
10 1 RO LOS Latched RX Channel 1: Coded 1 when asserted, Latched, Clears on Read.
10 0 RO LOS Latched RX Channel 0: Coded 1 when asserted, Latched, Clears on Read.
11-12 all RO Reserved: Coded 00h
13 7 RO High Internal Temperature Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
13 6 RO Low Internal Temperature Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
13 5-0 RO Reserved
14 7 RO High Internal 3.3 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 6 RO Low Internal 3.3 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 5-4 RO Reserved
14 3 RO High Internal 2.5 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 2 RO Low Internal 2.5 Vcc Alarm Latched: Coded 1 when asserted, Latched, Clears on Read.
14 1-0 RO Reserved
15-21 all RO Reserved: Coded 00h
22 7 RO High RX Power Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
22 6 RO Low RX Power Alarm Latched Channel 11: Coded 1 when asserted, Latched, Clears on Read.
22 5-4 RO Reserved
22 3 RO High RX Power Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
22 2 RO Low RX Power Alarm Latched Channel 10: Coded 1 when asserted, Latched, Clears on Read.
22 1-0 RO Reserved
23 7 RO High RX Power Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
23 6 RO Low RX Power Alarm Latched Channel 9: Coded 1 when asserted, Latched, Clears on Read.
23 5-4 RO Reserved
23 3 RO High RX Power Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
23 2 RO Low RX Power Alarm Latched Channel 8: Coded 1 when asserted, Latched, Clears on Read.
41 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
23 1-0 RO Reserved
24 7 RO High RX Power Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
24 6 RO Low RX Power Alarm Latched Channel 7: Coded 1 when asserted, Latched, Clears on Read.
24 5-4 RO Reserved
24 3 RO High RX Power Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
24 2 RO Low RX Power Alarm Latched Channel 6: Coded 1 when asserted, Latched, Clears on Read.
24 1-0 RO Reserved
25 7 RO High RX Power Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
25 6 RO Low RX Power Alarm Latched Channel 5: Coded 1 when asserted, Latched, Clears on Read.
25 5-4 RO Reserved
25 3 RO High RX Power Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
25 2 RO Low RX Power Alarm Latched Channel 4: Coded 1 when asserted, Latched, Clears on Read.
25 1-0 RO Reserved
26 7 RO High RX Power Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
26 6 RO Low RX Power Alarm Latched Channel 3: Coded 1 when asserted, Latched, Clears on Read.
26 5-4 RO Reserved
26 3 RO High RX Power Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
26 2 RO Low RX Power Alarm Latched Channel 2: Coded 1 when asserted, Latched, Clears on Read.
26 1-0 RO Reserved
27 7 RO High RX Power Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
27 6 RO Low RX Power Alarm Latched Channel 1: Coded 1 when asserted, Latched, Clears on Read.
27 5-4 RO Reserved
27 3 RO High RX Power Alarm Latched Channel 0: Coded 1 when asserted, Latched, Clears on Read.
27 2 RO Low RX Power Alarm Latched Channel 01: Coded 1 when asserted, Latched, Clears on Read.
27 1-0 RO Reserved
28 all RO Internal Temperature Monitor MSB: Integer part coded in signed 2’s complement. Tolerance is ± 3˚C.
29 all RO Internal Temperature Monitor LSB: Fractional part in units of 1˚/256 coded in binary.
30-31 all RO Reserved: Coded 00h
32-33 all RO Internal 3.3 Vcc Monitor: Voltage in 100 µV units coded as 16 bit unsigned integer,
Byte 32 is MSB. Tolerance is ± 0.1V.
34-35 all RO Internal 2.5 Vcc Monitor: Voltage in 100 µV units coded as 16 bit unsigned integer,
Byte 34 is MSB. Tolerance is ± 0.1V.
36-63 all RO Reserved: Code 00h.
64-65 all RO RX Optical Input, PAVE, Monitor Channel 11: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 64 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
66-67 all RO RX Optical Input, PAVE, Monitor Channel 10: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 66 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
68-69 all RO RX Optical Input, PAVE, Monitor Channel 9: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 68 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
70-71 all RO RX Optical Input, PAVE, Monitor Channel 8: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 70 is MSB. Tolerance is ± 3 dB for -10 to +2.4dBm range.
72-73 all RO RX Optical Input, PAVE, Monitor Channel 7: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 72 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
74-75 all RO RX Optical Input, PAVE, Monitor Channel 6: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 74 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
76-77 all RO RX Optical Input, PAVE, Monitor Channel 5: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 76 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
42 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
78-79 all RO RX Optical Input, PAVE, Monitor Channel 4: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 78 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
80-81 all RO RX Optical Input, PAVE, Monitor Channel 3: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 80 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
82-83 all RO RX Optical Input, PAVE, Monitor Channel 2: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 82 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
84-85 all RO RX Optical Input, PAVE, Monitor Channel 1: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 84 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
86-87 all RO RX Optical Input, PAVE, Monitor Channel 0: Optical power in 0.1 µW units coded as 16 bit unsigned
integer, Byte 86 is MSB. Tolerance is ± 3 dB for -10 to +2.4 dBm range.
88-89 all RO Elapsed (Power-on) Operating Time: Elapsed time in 2 hour units coded as 16 bit unsigned integer,
Byte 88 is MSB, Tolerance is ± 10%
90 all RWn Reserved: Coded 00h
91 7-1 RWv Reserved: Coded 0000000b
91 0 RWv Receiver Reset: Writing 1 return all registers except non-volatile RW to factory default values. Reads
0 after operation.
92 7-4 RWv Reserved: Coded 0000b
92 3 RWv RX Channel 11 Disable: Writing 1 deactivates the electrical output, Default is 0.
92 2 RWv RX Channel 10 Disable: Writing 1 deactivates the electrical output, Default is 0.
92 1 RWv RX Channel 9 Disable: Writing 1 deactivates the electrical output, Default is 0.
92 0 RWv RX Channel 8 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 7 RWv RX Channel 7 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 6 RWv RX Channel 6 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 5 RWv RX Channel 5 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 4 RWv RX Channel 4 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 3 RWv RX Channel 3 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 2 RWv RX Channel 2 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 1 RWv RX Channel 1 Disable: Writing 1 deactivates the electrical output, Default is 0.
93 0 RWv RX Channel 0 Disable: Writing 1 deactivates the electrical output, Default is 0.
94 7-4 RWv Reserved: Coded 0000b
94 3 RWv Squelch Disable Channel 11: Writing 1 inhibits squelch for the channel, Default is 0.
94 2 RWv Squelch Disable Channel 10: Writing 1 inhibits squelch for the channel, Default is 0.
94 1 RWv Squelch Disable Channel 9: Writing 1 inhibits squelch for the channel, Default is 0.
94 0 RWv Squelch Disable Channel 8: Writing 1 inhibits squelch for the channel, Default is 0.
95 7 RWv Squelch Disable Channel 7: Writing 1 inhibits squelch for the channel, Default is 0.
95 6 RWv Squelch Disable Channel 6: Writing 1 inhibits squelch for the channel, Default is 0.
95 5 RWv Squelch Disable Channel 5: Writing 1 inhibits squelch for the channel, Default is 0.
95 4 RWv Squelch Disable Channel 4: Writing 1 inhibits squelch for the channel, Default is 0.
95 3 RWv Squelch Disable Channel 3: Writing 1 inhibits squelch for the channel, Default is 0.
95 2 RWv Squelch Disable Channel 2: Writing 1 inhibits squelch for the channel, Default is 0.
95 1 RWv Squelch Disable Channel 1: Writing 1 inhibits squelch for the channel, Default is 0.
95 0 RWv Squelch Disable Channel 0: Writing 1 inhibits squelch for the channel, Default is 0.
96 7-6 RWv Rate Select Channel 11: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
96 5-4 RWv Rate Select Channel 10: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
43 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
96 3-2 RWv Rate Select Channel 9: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
96 1-0 RWv Rate Select Channel 8: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
97 7-6 RWv Rate Select Channel 7: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
97 5-4 RWv Rate Select Channel 6: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
97 3-2 RWv Rate Select Channel 5: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
97 1-0 RWv Rate Select Channel 4: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
98 7-6 RWv Rate Select Channel 3: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
98 5-4 RWv Rate Select Channel 2: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
98 3-2 RWv Rate Select Channel 1: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
98 1-0 RWv Rate Select Channel 0: Write 00 for max. BW (QDR 10 Gbps application),
01 for DDR and SDR BW (5 and 2.5 Gbps applications), rest reserved. Default is 00
99-105 all RWv Reserved: Coded 00h
106-111 all RWv Reserved: Coded 00h
112 7-4 RWv Reserved: Coded 0000b
112 3 RWv Mask LOS RX Channel 11: Writing 1 Prevents IntL generation, Default = 0
112 2 RWv Mask LOS RX Channel 10: Writing 1 Prevents IntL generation, Default = 0
112 1 RWv Mask LOS RX Channel 9: Writing 1 Prevents IntL generation, Default = 0
112 0 RWv Mask LOS RX Channel 8: Writing 1 Prevents IntL generation, Default = 0
113 7 RWv Mask LOS RX Channel 7: Writing 1 Prevents IntL generation, Default = 0
113 6 RWv Mask LOS RX Channel 6: Writing 1 Prevents IntL generation, Default = 0
113 5 RWv Mask LOS RX Channel 5: Writing 1 Prevents IntL generation, Default = 0
113 4 RWv Mask LOS RX Channel 4: Writing 1 Prevents IntL generation, Default = 0
113 3 RWv Mask LOS RX Channel 3: Writing 1 Prevents IntL generation, Default = 0
113 2 RWv Mask LOS RX Channel 2: Writing 1 Prevents IntL generation, Default = 0
113 1 RWv Mask LOS RX Channel 1: Writing 1 Prevents IntL generation, Default = 0
113 0 RWv Mask LOS RX Channel 0: Writing 1 Prevents IntL generation, Default = 0
114-115 all RWv Reserved: Coded 00h
116 7 RWv Mask Internal High Temperature Alarm: Writing 1 Prevents IntL generation, Default = 0
116 6 RWv Mask Internal Low Temperature Alarm: Writing 1 Prevents IntL generation, Default = 0
116 5-0 RWv Reserved
117 7 RWv Mask Internal High 3.3 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 6 RWv Mask Internal Low 3.3 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 5-4 RWv Reserved
117 3 RWv Mask Internal High 2.5 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 2 RWv Mask Internal Low 2.5 Vcc Alarm: Writing 1 Prevents IntL generation, Default = 0
117 1-0 RWv Reserved
118-122 all RWn Reserved
123-126 all RWv Reserved: Coded 00h
127 all RWv Page Select Byte
44 Avago Technologies Confidential – Restricted under NDA
RX Memory Map 00h Upper Page
Receiver serial ID page 00h entries and a description of the registers follow
Address Contents
Type Field Name/DescriptionByte Bit Code
128 all 00h RO Type Identifier: Coded 00h for unspecified. See SFF-8472 for reference
129 all 00000000b RO Module Description: Coded for < 1.5 W
130 all 11000000b RO Required Power Supplies: Coded for 3.3 V and 2.5 V supplies
131 all 01010101b RO Max Short-Term Operating Case Temperature in °C: Coded for 85 °C
132 all 00001100b RO Min Bit Rate in 100 Mb/s units: Coded for 1250 Mb/s
133 all 1100111b RO Max Bit Rate in 100 Mb/s units: Coded for 10312 Mb/s
134-135 all 00h RO Nominal Laser Wavelength (Wavelength in nm = value / 20): Coded 00h for RX
136-137 all 00h RO Wavelength deviation from nominal (tolerance in nm = ± value / 200): Coded
00h for RX
138 all 00101000b RO Supported Flags/Actions: Coded for RX LOS, Output Squelch for LOS, Alarm Flags
139 all 00110101b RO Supported Monitors: Coded for RX Input, Pave, Internal Temp, Elapsed Time
140 all 01100000b RO Supported Monitors: Coded for 3.3 V, 2.5 V
141 all 10101000b RO Supported Controls: Coded for Ch Disable, Squelch Disable, Rate Select
142 all 10100011b RO Supported Controls: Coded for RX Amplitude, RX De-emphasis, Ch Polarity Flip,
Addressing
143 all 00h RO Supported Functions
144-151 all 00h RO Reserved
152-167 all 41h 56h 41h
47h 4Fh 20h
20h x10
RO Vendor Name in ASCII: Coded AVAGO” for Avago Technologies, Spaces (20h) for
unused characters. Left justified.
168-170 all 00h 17h 6Ah RO Vendor OUI (IEEE ID): Coded “00h 17h 6Ah” for Avago Technologies
171-186 all 41h 46h
42h 52h
2Dh 37h
38h 44h
31h 33h
53h 5Ah
20h 20h
20h 20h
RO Vendor Part Number in ASCII: AFBR-78D13SZ . Left justified with spaces (20h)
for unused bytes
187-188 all 20h 20h RO Vendor Revision Number in ASCII: Coded with spaces (20h)
189-204 all RO Vendor Serial Number (ASCII): Varies by unit. Left justified with space (20h) for
unused bytes
205-212 all RO Vendor Date Code YYYYMMDD (ASCII)
213-222 all RO Customer Specific Area.
223 all RO Check sum addresses 128 through 222
224-255 all RO Vendor Specific
45 Avago Technologies Confidential – Restricted under NDA
RX Memory Map 01h Upper Page
Details of receiver upper page 01h follow.
Address
Type Field Name/DescriptionByte Bit
128 all RO Internal Temperature High Alarm Threshold MSB: Integer part coded in signed 2’s complement
129 all RO Internal Temperature High Alarm Threshold LSB: Fractional part in units of 1˚/256 coded in binary.
130 all RO Internal Temperature Low Alarm Threshold MSB: Integer part coded in signed 2’s complement
131 all RO Internal Temperature Low Alarm Threshold LSB: Fractional part in units of 1˚/256 coded in binary.
132-143 all RO Reserved
144-145 all RO Internal 3.3 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low
address is MSB.
146-147 all RO Internal 3.3 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low
address is MSB.
148-151 all RO Reserved
152-153 all RO Internal 2.5 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low
address is MSB.
154-155 all RO Internal 2.5 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low
address is MSB.
156-175 all RO Module Thresholds Reserved: Coded 00h
176-183 all RO Channel Thresholds Reserved: Coded 00h
184-185 all RO RX Optical Power All Channels High Alarm Threshold: Optical power in 0.1 µW units coded as 16 bit
unsigned integer, low address is MSB.
186-187 all RO RX Optical Power All Channels Low Alarm Threshold: Optical power in 0.1 µW units coded as 16 bit
unsigned integer, low address is MSB.
188-223 all RO Thresholds Reserved: Coded 00h
224 all RO Check sum: Low order 8 bits of the sum of all bytes from 128 through 223 inclusive
225 7-1 RWn Reserved: Coded 0000000b
225 0 RWn IntL Pulse/Static Option: Writing 1 sets IntL to Static mode, Default is 1 for Static mode
226 7-4 RWn Reserved: Coded 0000b
226 3 RWn Output Polarity Flip Channel 11: Writing 1 inverts truth of the differential output pair, Default is 0.
226 2 RWn Output Polarity Flip Channel 10: Writing 1 inverts truth of the differential output pair, Default is 0.
226 1 RWn Output Polarity Flip Channel 9: Writing 1 inverts truth of the differential output pair, Default is 0.
226 0 RWn Output Polarity Flip Channel 8: Writing 1 inverts truth of the differential output pair, Default is 0.
227 7 RWn Output Polarity Flip Channel 7: Writing 1 inverts truth of the differential output pair, Default is 0.
227 6 RWn Output Polarity Flip Channel 6: Writing 1 inverts truth of the differential output pair, Default is 0.
227 5 RWn Output Polarity Flip Channel 5: Writing 1 inverts truth of the differential output pair, Default is 0.
227 4 RWn Output Polarity Flip Channel 4: Writing 1 inverts truth of the differential output pair, Default is 0.
227 3 RWn Output Polarity Flip Channel 3: Writing 1 inverts truth of the differential output pair, Default is 0.
227 2 RWn Output Polarity Flip Channel 2: Writing 1 inverts truth of the differential output pair, Default is 0.
227 1 RWn Output Polarity Flip Channel 1: Writing 1 inverts truth of the differential output pair, Default is 0.
227 0 RWn Output Polarity Flip Channel 0: Writing 1 inverts truth of the differential output pair, Default is 0.
228 7-4 RWn RX Output Amplitude Control: Channel 11. See Code Description on page 47. Default = 0011b
228 3-0 RWn RX Output Amplitude Control: Channel 10. See Code Description on page 47. Default = 0011b
229 7-4 RWn RX Output Amplitude Control: Channel 9. See Code Description on page 47. Default = 0011b
229 3-0 RWn RX Output Amplitude Control: Channel 8. See Code Description on page 47. Default = 0011b
230 7-4 RWn RX Output Amplitude Control: Channel 7. See Code Description on page 47. Default = 0011b
230 3-0 RWn RX Output Amplitude Control: Channel 6. See Code Description on page 47. Default = 0011b
231 7-4 RWn RX Output Amplitude Control: Channel 5. See Code Description on page 47. Default = 0011b
231 3-0 RWn RX Output Amplitude Control: Channel 4. See Code Description on page 47. Default = 0011b
232 7-4 RWn RX Output Amplitude Control: Channel 3. See Code Description on page 47. Default = 0011b
232 3-0 RWn RX Output Amplitude Control: Channel 2. See Code Description on page 47. Default = 0011b
233 7-4 RWn RX Output Amplitude Control: Channel 1. See Code Description on page 47. Default = 0011b
233 3-0 RWn RX Output Amplitude Control: Channel 0. See Code Description on page 47. Default = 0011b
46 Avago Technologies Confidential – Restricted under NDA
Address
Type Field Name/DescriptionByte Bit
234 7-4 RWn RX Output De-emphasis Control: Channel 11. See Code Description on page 47. Default = 0000b
234 3-0 RWn RX Output De-emphasis Control: Channel 10. See Code Description on page 47. Default = 0000b
235 7-4 RWn RX Output De-emphasis Control: Channel 9. See Code Description on page 47.. Default = 0000b
235 3-0 RWn RX Output De-emphasis Control: Channel 8. See Code Description on page 47. Default = 0000b
236 7-4 RWn RX Output De-emphasis Control: Channel 7. See Code Description on page 47. Default = 0000b
236 3-0 RWn RX Output De-emphasis Control: Channel 6. See Code Description on page 47. Default = 0000b
237 7-4 RWn RX Output De-emphasis Control: Channel 5. See Code Description on page 47. Default = 0000b
237 3-0 RWn RX Output De-emphasis Control: Channel 4. See Code Description on page 47. Default = 0000b
238 7-4 RWn RX Output De-emphasis Control: Channel 3. See Code Description on page 47. Default = 0000b
238 3-0 RWn RX Output De-emphasis Control: Channel 2. See Code Description on page 47. Default = 0000b
239 7-4 RWn RX Output De-emphasis Control: Channel 1. See Code Description on page 47. Default = 0000b
239 3-0 RWn RX Output De-emphasis Control: Channel 0. See Code Description on page 47. Default = 0000b
240-243 all RWn Reserved Controls: Coded 00h
244-249 all RWv Reserved Masks: Coded 00h
250 7 RWv Mask High RX Power Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
250 6 RWv Mask Low RX Power Alarm Channel 11: Writing 1 Prevents IntL generation, Default = 0
250 5-4 RWv Reserved
250 3 RWv Mask High RX Power Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
250 2 RWv Mask Low RX Power Alarm Channel 10: Writing 1 Prevents IntL generation, Default = 0
250 1-0 RWv Reserved
251 7 RWv Mask Bt High RX Power Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
251 6 RWv Mask Low RX Power Alarm Channel 9: Writing 1 Prevents IntL generation, Default = 0
251 5-4 RWv Reserved
251 3 RWv Mask High RX Power Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
251 2 RWv Mask Low RX Power Alarm Channel 8: Writing 1 Prevents IntL generation, Default = 0
251 1-0 RWv Reserved
252 7 RWv Mask High RX Power Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
252 6 RWv Mask Low RX Power Alarm Channel 7: Writing 1 Prevents IntL generation, Default = 0
252 5-4 RWv Reserved
252 3 RWv Mask High RX Power Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
252 2 RWv Mask Low RX Power Alarm Channel 6: Writing 1 Prevents IntL generation, Default = 0
252 1-0 RWv Reserved
253 7 RWv Mask High RX Power Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
253 6 RWv Mask Low RX Power Alarm Channel 5: Writing 1 Prevents IntL generation, Default = 0
253 5-4 RWv Reserved
253 3 RWv Mask High RX Power Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
253 2 RWv Mask Low RX Power Alarm Channel 4: Writing 1 Prevents IntL generation, Default = 0
253 1-0 RWv Reserved
254 7 RWv Mask High RX Power Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
254 6 RWv Mask Low RX Power Alarm Channel 3: Writing 1 Prevents IntL generation, Default = 0
254 5-4 RWv Reserved
254 3 RWv Mask High RX Power Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
254 2 RWv Mask Low RX Power Alarm Channel 2: Writing 1 Prevents IntL generation, Default = 0
254 1-0 RWv Reserved
255 7 RWv Mask High RX Power Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
255 6 RWv Mask Low RX Power Alarm Channel 1: Writing 1 Prevents IntL generation, Default = 0
255 5-4 RWv Reserved
255 3 RWv Mask High RX Power Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
255 2 RWv Mask Low RX Power Alarm Channel 0: Writing 1 Prevents IntL generation, Default = 0
255 1-0 RWv Reserved
47 Avago Technologies Confidential – Restricted under NDA
Receiver Output Amplitude Control Code Description
Control registers 228 through 233 permit output signal peak amplitude selection. Four bit code blocks (either bits 7
through 4 or 3 through 0 where bit 7 or 3 is the MSB) are assigned to each channel. Codes 1xxx are reserved. Code 0111
calls for full scale peak signal amplitude and code 0000 calls for minimum signal amplitude. See the following table for
receiver output amplitude control settings.
Code
Receiver Output Amplitude – Default De-emphasis
ReferenceMin Nominal Max Units
1xxxb Reserved
0111b 640 800 960 mVppd Full Scale
0110b 560 700 840 mVppd
0101b 480 600 720 mVppd
0100b 400 500 600 mVppd
0011b 320 400 480 mVppd Default setting
0010b 240 300 360 mVppd
0001b 150 200 250 mVppd
0000b 70 100 130 mVppd
Receiver Output De-emphasis Control Code Description
Control registers 234 through 239 permit output de-emphasis selection. Four bit code blocks (either bits 7 through 4
or 3 through 0 where bit 7 or 3 is the MSB) are assigned to each channel. Codes 1xxx are reserved. 1 Code 0111 calls for
full scale, 100% de-emphasis and code 0000 calls for no de-emphasis. Intermediate code values yield intermediate de-
emphasis levels. The total dynamic range of de-emphasis control is 6 dB.
Code De-emphasis % Reference
1xxxb Reserved
0111b 100 Full Scale
0110b
0101b
0100b
0011b
0010b
0001b
0000b 0 Default setting
48 Avago Technologies Confidential – Restricted under NDA
Serial ID 00h Upper Page Description
Description of Serial id page 00h codes follows.
Byte 128 Module Type
Address
Code
Field Name/Description
Byte Module Type
128 Type Identifier: See SFF-8472 for reference, also SFP and XFP MSA, Coded 00h if unspecified.
Byte 129 Module Description
Address
Code Field Name/DescriptionByte Bit
129 7-6 00b Power Class 1: Module Power Consumption < 1.5 W
7-6 01b Power Class 2: Module Power Consumption < 2.0 W
7-6 10b Power Class 3: Module Power Consumption < 2.5 W
7-6 11b Power Class 4: Module Power Consumption < 3.5 W
5 Coded 1 for TX CDR provided; else coded 0
4 Coded 1 for RX CDR provided; else coded 0
3 Coded 1 for Required Reference Clock; else coded 0
2 Coded 1 for Page 02 provided; else coded 0
1 Coded 1 for Controlled Launch Transmitter (TIA 492AAAC); else coded 0
0 Reserved
Byte 130 Module Description: Required Power Supplies
Address
Code Field Name/DescriptionByte Bit
130 7 3.3 V, Coded 1 if required, else coded 0.
6 2.5 V, Coded 1 if required, else coded 0.
5 1.8 V, Coded 1 if required, else coded 0.
4 Vo Supply, Coded 1 if required, else coded 0.
3 Variable Supply, Coded 1 if required, else coded 0.
2-0 Reserved
Byte 131 Module Description: Max Recommended Operating Case Temperature
Address
Code Field Name/DescriptionByte Bit
131 Max Tc = binary value x 1.0 °C
Byte 132 Module Description Min Signal Rate per channel
Address
Code Field Name/DescriptionByte
132 00h Unknown/unspecified
rest Min Signal Rate = binary value x 100 Mb/s
49 Avago Technologies Confidential – Restricted under NDA
Byte 133 Module Description Max Signal Rate per channel
Address
Code Field Name/DescriptionByte
133 00h Unknown/unspecified
Max Signal Rate = binary value x 100 Mb/s
Byte 134 - 137 Module Description Wavelength and Tolerance
Address
Code Field Name/DescriptionByte
134-135 Nominal Center Wavelength: Wavelength in nm = binary value / 20, Coded 00b if unspecified/
unused.
136-137 Wavelength Tolerance: Tolerance in nm = ± binary value / 200, Coded 00b if unspecified/unused.
Byte 138 Supported Functions – Flags/Actions
Address
Code Field Name/DescriptionByte Bit
138 7 Coded 1 for TX Fault Flag provided, else coded 0
6 Coded 1 for TX LOS Flag provided, else coded 0
5 Coded 1 for RX LOS Flag provided, else coded 0
4 Coded 1 for CDR LOL Flag provided, else coded 0
3 Coded 1 for Output Squelch for LOS provided, else coded 0
2 Coded 1 for Monitor Alarm and Warning Flags provided, coded 0 for Monitor Alarm Flags pro-
vided
1-0 Reserved
Byte 139 - 140 Supported Functions - Monitors
Address
Code Field Name/DescriptionByte Bit
139 7 Coded 1 for TX Bias Monitor, else coded 0
139 6 Coded 1 for TX LOP Monitor, else coded 0
139 5 Coded 1 for individual RX Input Power Monitors, coded 0 for single-channel or group monitor
139 4 Coded 1 for RX Input Power reported as Pave, coded 0 for reported as OMA 21
139 3 Coded 1 for Case Temperature Monitor, else coded 0
139 2 Coded 1 for Internal Temperature Monitor, else coded 0
139 1 Coded 1 for Peak Temperature Monitor, else coded 0
139 0 Coded 1 for Elapsed Time Monitor, else coded 0
140 7 Coded 1 for BER Monitor, else coded 0
140 6 Coded 1 for Internal 3.3 V Vcc Monitor, else coded 0
140 5 Coded 1 for Internal 2.5 V Vcc Monitor, else coded 0
140 4 Coded 1 for Internal 1.8 V Vcc Monitor, else coded 0
140 3 Coded 1 for Internal Vo Vcc Monitor, else coded 0
140 2 Coded 1 for TEC current Monitor, else coded 0
140 1-0 Reserved
50 Avago Technologies Confidential – Restricted under NDA
Byte 141 Supported Functions – Controls
Address
Code Field Name/DescriptionByte Bit
141 7-6 00 Channel Disable Control not provided/unspecified
7-6 01 Global Channel Disable Control implemented
7-6 10 Individual and independent Channel Disable Control implemented
7-6 11 Reserved
5-4 00 Squelch Disable Control not provided/unspecified
5-4 01 Global Squelch Disable Control implemented
5-4 10 Individual and independent Channel Squelch Control implemented
5-4 11 Reserved
3-2 00 Rate Select Control not provided/unspecified
3-2 01 Global Rate Select Control implemented
3-2 10 Individual and independent Rate Select Control implemented
3-2 11 Reserved
1-0 00 TX Input Equalization Control not provided/unspecified
1-0 01 Global TX Input Equalization Control implemented
1-0 10 Individual and independent TX Input Equalization Control implemented
1-0 11 Reserved
Byte 142 Supported Functions – Controls
Address
Code Field Name/DescriptionByte Bit
142 7-6 00 RX Output Amplitude Control not provided/unspecified
7-6 01 Global RX Output Amplitude Control implemented
7-6 10 Individual and independent RX Output Amplitude Control implemented
7-6 11 Reserved
5-4 00 RX Output De-emphasis Control not provided/unspecified
5-4 01 Global RX Output De-emphasis Control implemented
5-4 10 Individual and independent RX Output De-emphasis Control implemented
5-4 11 Reserved
3 Coded 1 for TX Margin Mode provided, else coded 0
2 Coded 1 for Channel Reset Control provided, else coded 0
1 Coded 1 for Channel Polarity Flip Control provided, else coded 0
0 Coded 1 for Module Addressing Control provided, else coded 0
51 Avago Technologies Confidential – Restricted under NDA
Byte 143 Supported Functions
Address
Code Field Name/DescriptionByte Bit
143 7 Coded 1 for FEC Control, else coded 0
6 Coded 1 for PEC Control, else coded 0
5 Coded 1 for JTAG Control, else coded 0
4 Coded 1 for AC-JTAG Control, else coded 0
3 Coded 1 for BIST, else coded 0
2 Coded 1 for TEC Temperature Control, else coded 0
1 Coded 1 for Sleep/Sensor Mode Set Control provided, else coded 0
0 Coded 1 for CDR Bypass Control provided, else coded 0
Byte144 - 151 Reserved
Address
Code Field Name/DescriptionByte Bit
144-151 Reserved: Coded 00h
Byte 152 - 221 Vendor Information
Address
Code Field Name/DescriptionByte Bit
152-167 Vendor Name ASCII – 16 bytes. Left justified with space (20h) for unused bytes
168-170 Vendor OUI – 3 bytes; Unspecified where coded all zeroes
171-186 Vendor Part Number ASCII – 16 bytes. Left justified with space (20h) for unused bytes
187-188 Vendor Revision Number ASCII – 2 bytes
189-204 Vendor Serial Number ASCII – 16 bytes. Left justified with space (20h) for unused bytes
205-212 Vendor Date Code ASCII – 8 bytes; coded YYYYMMDD
213-222 Customer Specific Area – 10 bytes; Left justified with space (20h) for unused bytes
Byte 223 Check Sum for bytes 128 through 222
Address
Code Field Name/DescriptionByte Bit
223 Check Code – 1 byte: Low order 8 bits of the sum of all bytes from 128 through 222 inclusive.
Byte 224 - 255 Vendor Specific
Address
Code Field Name/DescriptionByte Bit
224-239
240-253 Vendor Specific – 14 bytes
254-255 All Reserved
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52 Avago Technologies Confidential – Restricted under NDA
Appendix A: Module Mechanical Drawing
Figure A1. Module Top and Side View
Pin A1 Location indicator (see Fig. B2)
Channel 11
Channel 0
(7.591)
2x ø0.702±0.001
a! x (0130025 SOLDER MASK OPENING I I [SEE NOTE I I AND 12} run All GREEK AlPHABl‘l an x we) 0 020 GOLD PAD DIMENSIONS m um I 5,7392 E CONVACT PAD"JT" CONTACT o 7424 FE“? EE 2x 3300:0075 CONTACY PAD "AI” IEE _ ( 7 50] 2 we I 2x 4 I00:0.075 ( 6'20] Ema Em zxw SEE NOYE Vk/J—l 2x 100145200500 AVGGO vscnuoLomss
Avago Technologies Confidential – Restricted under NDA
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-4372EN - March 18, 2014
Figure A2. Pin A1 Location
Note the fiber exit
direction relative
to Pin A1 location
indicator
Channel 0
Channel 11

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