ams Datasheet Page 1
[v2-06] 2014-Oct-14 Document Feedback
AS5050A
Low Power 10-Bit Magnetic Position
Sensor
The AS5050A is a single-chip on-axis magnetic rotary position
sensor with low voltage and low power features.
It includes an integrated Hall element array, a high resolution
ADC and a smart power management controller.
The angle position, alarm bits and magnetic field information
are transmitted over a 3-wire or 4-wire SPI interface to the
microcontroller.
The AS5050A is available in a compact QFN 16-pin 4x4x0.85 mm
package and specified over an operating temperature of -40ºC
to 85ºC.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5050A, Low Power 10-Bit
Magnetic Position Sensor are listed below:
Figure 1:
Added Value of Using AS5050A
Benefits Features
Precise and reliable absolute angle measurement 10-Bit absolute angle position indication
Very low power consumption 3μA current consumption in low power mode
High reliability sensing Immune to external magnetic stray fields
Synchronization between microcontroller and sensor Interrupt pin displays availability of new data
Ideal for small and compact designs QFN-16 4x4 package
Industry-standard interface 3- or 4-wire SPI interface
General Description
ATAN (comm)
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AS5050A − General Description
Applications
This sensor is optimized for a broad range of demanding
applications including:
•Servo motor control
Battery operated systems
• Robotics
Block Diagram
The functional blocks of this sensor are
shown below:
Figure 2:
AS5050A Block Diagram
ADC
AS5050A
VDD
VSS
SS/
MOSI
SCK
MISO
Analog
Front-End
ATAN
(CORDIC)
AGC
INT/
EN_INT/
Hall Sensors
Low Power Management
VDDp WM
SPI
Test
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AS5050A − Pin Assignment
The AS5050A pin assignments are shown below.
Figure 3:
Pin Diagram
Figure 4:
Pin Description
Pin Assignments (Top View):
Package drawing is not to scale.
Pin Number Name Type Description
1MOSI Digital input SPI bus data input
2MISO Digital output, tri-state buffer SPI bus data output
3SCK Digital input Schmitt trigger SPI clock
4SS/ Digital input SPI Slave Select, active low
5NC
-Leave unconnected
6NC
7NC
8NC
9Test Analog Test pin, connect to VSS
10 EN_INT/ Digital input Enable interrupt, active low
Pin Assignment
MOSI
MISO
SCK
SS/
16 131415
5 876
1
4
3
2
12
9
10
11
VDD
VDDp
EN_INT/
Test
NC
NC
NC
NC
NC
VSS
WM
INT/
Epad
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AS5050A − Pin Assignment
11 VDDp
Supply
Peripheral power supply, 1.8V to VDD
12 VDD Analog and digital power supply, 3.0V to
3.6V
13 VSS Ground
14 WM Digital I/O Low: 3-wire mode
High: 4-wire mode
15 INT/ Digital output, tri-state buffer Interrupt output. Active LOW, when
conversion is finished
16 NC -Leave unconnected
Epad - - Exposed pad, leave unconnected
Pin Number Name Type Description
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AS5050A − Absolute Maximum Ratings
Stresses beyond those listed in Absolute Maximum Ratings” on
page 5 may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at
these or any other conditions beyond those indicated in
“Electrical Characteristics” on page 6 is not implied. Exposure
to absolute maximum rating conditions for periods may affect
device reliability.
Figure 5:
Absolute Maximum Ratings
Symbol Parameter Min Max Units Comments
Electrical Parameters
VDD DC supply voltage -0.3 5.0 V
VDDp Peripheral supply voltage -0.3 VDD+0.3 V
VIN Input pin voltage -0.3 5.0 V
Iscr Input current (latchup
immunity) -100 100 mA Norm: JEDEC 78
Electrostatic Discharge
ESD Electrostatic discharge ±1 - kV Norm: MIL-STD-883 E method
3015
Continuous Power Dissipation
ΘJA Package thermal resistance - 33.5 °C/W Velocity=0, Multi Layer PCB;
JEDEC Standard Testboard
PtTotal power dissipation 36 mW
Temperature Ranges and Storage Conditions
Tstrg Storage temperature -55 125 °C
TBODY Package body temperature 260 °C
The reflow peak soldering
temperature (body temperature)
specified is in accordance with
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity
Classification for Non-Hermetic
Solid State Surface Mount
Devices”.
The lead finish for Pb-free leaded
packages is matte tin (100% Sn).
Humidity non-condensing 5 85 %
MSL Moisture Sensitive Level 3 Represents a maximum floor life
time of 168h
Absolute Maximum Ratings
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AS5050A − Electrical Characteristics
Operating Conditions
Figure 6:
Operating Conditions
System Parameters
Figure 7:
System Parameters
Symbol Parameter Conditions Min Max Units
VDD DC supply voltage 3.0 3.6 V
VDDp Peripheral supply voltage 1.8 VDD V
VIN Input pin voltage -0.3 VDDp +0.3 V
Tamb Ambient operating
temperature -40 85 °C
External components
Power supply filter, pin VDD
(see “Power Supply Filter
on page 10)
2.2 4.7 μF
15 33 Ω
Ceramic capacitor, pin VDDp
to VSS 100 nF
Symbol Parameter Conditions Min Typ Max Units
ION Current consumption Normal operating mode 8.5 mA
IOFF Current consumption
Low power mode with activated
POR
(POR_OFF = 0x00) – default
setting
33 μA
Low power mode with
deactivated POR
(POR_OFF = 0x5A)
A
treadout Readout rate Time between READ ANGLE
command and INTERRUPT 500 μs
tPwrUp Power up time Minimum time after power up
before the sensor is operational 580 μs
RdLateral displacement
range
Misalignment of the center of the
magnet to the center of the die ±0.5 mm
BZMagnetic input field 30 90 mT
BZ00 Magnetic input field
range Gain = 00 58 90 mT
Electrical Characteristics
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AS5050A − Electrical Characteristics
DC/AC Characteristics
Digital pads: MISO, MOSI, SCK, SS/, EN_INT/, INT/, WM
Figure 8:
DC/AC Characteristics
BZ01 Magnetic input field
range Gain = 01 51 80 mT
BZ10 Magnetic input field
range Gain = 10 39 62 mT
BZ11 Magnetic input field
range Gain = 11 30 47 mT
N00 Noise (rms) Within Bz00 magnetic input field
range and Gain = 00 0.128 degrms
N01 Noise (rms) Within Bz01 magnetic input field
range and Gain = 01 0.149 degrms
N10 Noise (rms) Within Bz10 magnetic input field
range and Gain = 10 0.192 degrms
N11 Noise (rms) Within Bz11 magnetic input field
range and Gain = 11 0.256 degrms
INL Integral Non Linearity
Using Bomatec 6x2.5 mm NdFeB
magnet with a maximum
x/y-displacement radius of 250
μm from package center
-1.41 1.41 deg
RPU/PD Recommended pull-up
or pull-down resistor
Applicable for daisy chain
configuration 10k 50k Ω
Symbol Parameter Conditions Min Max Units
VIH High level input voltage 0.7 * VDDp V
VIL Low level input voltage VDDp > 2.7V 0.3 * VDDp V
VIL Low level input voltage VDDp < 2.7V 0.25 * VDDp V
ILEAK Input leakage current 1 μA
VOH High level output voltage VDDp - 0.5 V
VOL Low level output voltage VSS + 0.4 V
CLCapacitive load 35 pF
Symbol Parameter Conditions Min Typ Max Units
2:! ya
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AS5050A − Detailed Description
Noise Performance
This figure shows the Worst Case Noise Performance of the
AS5050A at different gain settings which can be set in the
System Configuration Register 1.
Figure 9:
Worst Case Noise Performance of the AS5050A
Detailed Description
rms Noise [degrees]
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0 102030405060708090100
N 11
N 10
N 01
N 00
Bz [mT]
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AS5050A − Detailed Description
Typical Application
The AS5050A uses on-chip Hall elements to convert the
magnetic field component perpendicular to the surface of the
chip into a voltage.
The signals from the Hall elements are amplified and filtered by
the analog front-end (AFE) before being converted by the
analog-to-digital converter (ADC). The output of the ADC is
processed by the hardwired CORDIC (coordinate rotating
digital computer) block to compute the angle and magnitude
of the magnetic vector. The intensity of the magnetic field
(magnitude) is used by the automatic gain control (AGC) to
adjust the amplification level for compensation of temperature
and magnetic field variations.
The internal 10-Bit resolution is available by reading a register
through the SPI interface. The IC settings in the AS5050A can
be programmed through the SPI interface without any
dedicated programmer.
Figure 10:
Typical Application Using SPI 4-Wire Mode and INT/ Output
Figure 10 shows how the AS5050A can be connected to a
microcontroller. The SPI interface is a slave interface for
accessing the on-chip registers. The INT/ output is an active-low
interrupt for informing the host microcontroller when a new
result is available.
ADC
AS5050A
VDD
VSS
SS/
MOSI
SCK
MISO
Analog
Front-End
ATAN
(CORDIC)
AGC
INT/
EN_INT/
Hall Sensors
Low Power Management
VDDp WM
SPI
Test
µC
4.7µF 15 R
DC 3.0V – 3.6V DC 1.8V – 3.6V
SPI
Interface
Interrupt
100nF
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AS5050A − Detailed Description
Power Supply Filter
Due to the sequential internal sampling of the Hall sensors,
fluctuations on the analog power supply (pin#12: VDD) may
cause additional jitter of the measured angle. This jitter can be
avoided by providing a stable VDD supply.
The easiest way to achieve that is to add a RC filter: 15Ω in series
and 4.7μF to ground as shown in Figure 10.
Alternatively, a filter: 33Ω + 2.2μF may be used. However with
this configuration, the minimum supply voltage is 3.15V.
Reading an Angle
Sending a READ ANGLE command through the SPI interface
automatically powers up the chip, drives INT/ high and starts
another angle measurement. The completion of the angle
measurement is indicated by driving the INT/ output low and
clearing the WOW flag in the error status register. The
microcontroller can respond to the interrupt by reading the
angle value from the AS5050A over the SPI interface. (See
Figure 11).
A READ ANGLE command must not be sent while a
measurement is being performed as indicated by INT/ driven
high or WOW = 1.
Reducing the Angle Jitter
The chip only performs a single angle measurement after a
READ ANGLE command is received, after which it returns to
low-power mode, so it is in normal operating mode for only a
very short time (tPwrUp).
The angle jitter can be reduced by averaging several angle
measurements in the microcontroller. For example, an
averaging of four samples reduces the jitter by 6dB (50%).
Operating Modes
After a READ ANGLE command is sent, the angle is measured
and internal calculations are started. During this time (normal
operating mode) the INT/ output is high until the device finishes
the calculations and a second READ ANGLE command may not
be sent.
After the INT/ output is driven low the device goes into
low-power mode. If the microcontroller doesn't monitor the
INT/ output a minimum guard time (treadout) must be inserted
before the next READ ANGLE command can be sent.
After startup the AS5050A has higher power consumption than
during low-power mode. When the POR cell is deactivated the
chip uses less current during low-power mode (see POR OFF
Register).
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AS5050A − Detailed Description
Figure 11:
Operating Modes
Note(s) and/or Footnote(s):
1. Even in low power mode, the power supply must be capable of supporting the active current (Ion) at least for maximum treadout,
until the AS5050A is suspended to low power mode.
Daisy Chain
The AS5050A allows a Daisy Chain configuration as shown in
Figure 21.
In this configuration the microcontroller can read multiple
AS5050A chips using only 5 wires.
Read angle Read angle
MOSI
CS/
INT/
Normal operating mode
Communication
mode Low power mode Communication
mode
Operating mode
treadout
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AS5050A − SPI Interface
The 16-bit SPI interface provides read/write access to the
on-chip registers. The interface only supports slave operation
mode. It communicates at clock rates up to 10 MHz.
The AS5050A SPI uses mode=1 (CPOL=0, CPHA=1) to exchange
data. As shown in Figure 12, a data transfer starts with the
falling edge of CSn (SCL is low). The AS5050A samples the MOSI
input on the falling edge of SCL. SPI commands are executed at
the end of the frame (rising edge of CSn). The bit order is MSB
first. Data is protected by parity.
SPI Timing
Figure 12:
SPI Timing Diagram
SPI Interface
CSn
(Input)
CLK
(Input)
MOSI
(Input)
MISO
(Output)
tclk
tL
tMOSI
tMISO tOZ
tOZ
tH
tCSn
tclkL tclkH
data[15]
data[15] data[14]
data[14]
data[0]
data[0]
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AS5050A − SPI Interface
Figure 13:
SPI Timing
Note(s) and/or Footnote(s):
1. If the previous command was a READ ANGLE command (0x3FFF) a minimum time of readout has to be waited before sending a next
READ ANGLE command. (see Operating Modes” on page 10)
SPI Wire Mode Selection
The SPI interface can be set in two different modes: 3-wire mode
or 4-wire mode.
Figure 14:
Wire Mode Selection
Parameter Description Min Max Unit
tLTime between CSn falling edge and CLK rising edge 50 ns
tclk Serial clock period 100 ns
tclkL Low period of serial clock 50 ns
tclkH High period of serial clock 50 ns
tHTime between last falling edge of CLK and rising edge
of CSn 50 ns
tCSn High time of CSn between two transmissions (1) 50 ns
tMOSI Data input valid to falling clock edge 20 ns
tMISO CLK edge to data output valid 35 ns
tOZ Release bus time after CS rising edge. 50 ns
WM (Pin 14) Connection option
03-wire mode
14-wire-mode
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AS5050A − SPI Interface
SPI Transaction
An SPI transaction consists of a 16-bit command frame followed
by a 16-bit data frame. Figure 15 shows the structure of the
command frame.
SPI Command Frame
Figure 15:
SPI Command Frame
To increase the reliability of communication over the SPI, an
even parity bit (PAR) must be generated and sent. A wrong
setting of the parity bit causes the PARITY bit in the error status
register of the AS5050A to be set. The parity bit is calculated
from the upper 15-bits of the command frame. The 16-bit
command specifies the address and whether the transaction is
a read or a write.
Bit 15 1413121110987654321 0
R/W Address 14:1 PAR
Bit Name Description
15 R/W 0=Write, 1=Read
14:1 Address 14 bit address to read or write
0 PAR Parity bit (even) calculated on the upper 15 bits
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AS5050A − SPI Interface
SPI Read Data Frame
Figure 16:
SPI Read Data Frame
The data is sent from the AS5050A to the microcontroller on the
MISO output. The parity bit PAR is calculated for the upper 15
bits. If an error is detected in the previous SPI command frame,
the EF bit is set. The addressed register is sampled on the rising
edge of CSn and the data is transmitted on MISO with the next
read command, as shown in Figure 17.
Figure 17:
SPI Read
Bit 15 1413121110 9 8 7 6 5 4 3 2 1 0
Data 15:2 EF PAR
Bit Name Description
15:2 Data 14 bit read data
1 EF 0 = no command frame error occurred, 1 = error occurred
0 PAR Parity bit (even) calculated on the upper 15 bits
Read ADD[n] Read ADD[k]
CSn
Read ADD[p]
Data ADD[n] Data ADD[p]
Read ADD[m]
Data ADD[k]
Command CommandCommand Command
Data DataData
MOSI
MISO
Ea fix > > ] : :\ : l ( H H \ \ \ \ \ \ \ \ \ \ \ \
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AS5050A − SPI Interface
SPI Write Data Frame
Figure 18:
SPI Write Data Frame
The parity bit PAR is calculated for the upper 15 bits.
In a SPI write transaction, the write command frame (e.g. Write
ADD[n]) is followed by a data frame (e.g. DATA [x]). In addition
to writing an address in the AS5050A, a write command frame
causes the old contents of the addressed register (e.g. DATA [y])
to be sent on MISO in the following frame. This is followed by
the new contents of the addressed register (DATA [x]) as shown
in Figure 19.
Figure 19:
SPI Write Transaction
Bit 15 1413121110987654321 0
Data 15:2 DC PAR
Bit Name Description
15:2 Data 14 bit write data
1 DC Don’t Care
0 PAR Parity bit (even) calculated on the upper 15 bits
Write ADD[n] DATA(x)
CSn
Write ADD[m]
Data ADD[n] Data ADD[m]DATA(x)
Command CommandData to write into ADD[n]
Data content ADD[n] Data content ADD[m]
New Data content
of ADD[n]
MOSI
MISO
DATA(y)
Data to write into ADD[m]
Next
command
Command
DATA(y)
New Data content
of ADD[m]
E E E E |:||:||:||:| |:||:||:||:|
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AS5050A − SPI Interface
SPI Connection to the microcontroller
Figure 20:
Single Slave Mode
µC AS5050A
MOSI
MISO
SCK
SS/
INT/
MOSI
MISO
SCK
SS/
INT/
Wire Mode
µC AS5050A
4 wire mode
MISO Angle 1 Angle 2 Angle 3
MOSI 0xFFFF
Read angle 1
0xFFFF
Read angle 2
0xFFFF
Read angle 3
0xFFFF
Read angle 4
SS/
MISO
SS/
3 wire mode (Read only)
Angle 1 Angle 2 Angle 3
1
MOSI
MISO
SCK
SS/
INT/
Wire Mode
0xFFFF
MOSI
MISO
SCK
SS/
INT/
1
µC AS5050A
MISO
SS/
3 wire mode (Bi-Directional)
0xFFFF
Read angle 1 Angle 1 0xFFFF
Read angle 2 Angle 2
MOSI
MISO
SCK
SS/
INT/
Wire Mode
MOSI
MISO
SCK
SS/
INT/
0
INT/
INT/
INT/
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AS5050A − SPI Interface
Daisy Chain, 4 Wire
Figure 21:
Daisy Chain, 4 Wire
µC
AS5050A
1
INT/
MOSI
MISO
SCK
SS/
MOSI
MISO
SCK
SS/
Wire Mode
En_INT/
AS5050A
2
MOSI
MISO
SCK
SS/
Wire Mode
En_INT/
AS5050A
3
MOSI
MISO
SCK
SS/
Wire Mode
En_INT/
1
0
1
1
INT/
INT/
INT/
MISO
MOSI 0xFFFF
Read angle 3
0xFFFF
Read angle 2
0xFFFF
Read angle 1
SS/
Angle 3 Angle 2 Angle 1
0xFFFF
Read angle 3
0xFFFF
Read angle 2
0xFFFF
Read angle 1
INT/
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AS5050A − Registers
The on-chip registers are shown in Figure 22.
Figure 22:
Registers
POR OFF (0x3F22)
Writing the value 0x5A to the POR OFF Register (0x3F22)
deactivates the POR cell and reduces the current consumption
in low power mode (IOFF).
Software Reset (0x3C00)
Writing to the Software Reset Register initiates a Software
Reset. With the RES SPI bit of the Data Package set to 1 it is
possible to reset the SPI registers. After a software reset a new
angle conversion is started; this is needed to set the AS5050A
into an initial state. This angle is not readable by the
microcontroller.
The AS5050A is ready as soon as INT/ is driven low or a minimum
time (treadout) has elapsed.
Figure 23:
Software Reset Command
Name Address Bits Mod Default Description
POR OFF 0x3F22 7:0 R/W 0x0000 Power On Reset OFF
Software Reset 0x3C00 13:0 W 0x0000 Software Reset
Master Reset 0x33A5 13:0 W 0x0000 Master Reset
Clear EF 0x3380 13:0 R 0x0000 Clear Error Flag
NOP 0x0000 13:0 W 0x0000 No Operation
AGC 0x3FF8 5:0 R/W 0x0020 Automatic Gain Control
Angular Data 0x3FFF 13:0 R 0x0000 Measured Angle
Error Status 0x335A 13:0 R 0x0000 Error Status Register
System Config 0x3F20 9:13 R/W 0x000 System Configuration Register 1
Bit 1514131211109876543 2 1 0
Content011 11000000000 0PAR
Registers
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AS5050A − Registers
Figure 24:
Data Package
Master Reset (0x33A5)
Writing to the Master Reset Register initiates a Master Reset.
This is similar to the Software Reset with the difference that no
data package is needed.
Figure 25:
Master Reset Command
Clear Error Flag (0x3380)
Reading from the Clear Error Flag Register clears the Error Flag
which is contained in every Read Data Frame. The Read data is
0x0000 which indicates a successful clear command.
Figure 26:
Clear Error Flag Command
Bit151413121110 9 8 76 5 4 3 2 1 0
DC RES
SPI DC PAR
Bit Name Description
15:3 DC Don’t Care
2 RES SPI If set to 1 the SPI registers are reset as well
1 DC Don’t Care
0 PAR Parity bit (even) calculated on the upper 15 bits
Bit 1514131211109876543 2 1 0
Content011 00111010010 1PAR
Bit 1514131211109876543 2 1 0
Content111 00111000000 0PAR
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AS5050A − Registers
Possible Conditions which force the Error Flag to be set:
Wrong parity
Wrong command
Wrong number of clocks
Note(s): If the error flag is set to 1 because of a communication
problem the flag remains set until a Clear Error Flag Command
is executed.
No Operation (0x0000)
The No Operation (NOP) command represents a dummy write
to the AS5050A. If no error happens the chip responds with
0x0000.
Figure 27:
NOP Command
AGC – Automatic Gain Control (0x3FF8)
Writing a value different than zero to this register, stops the AGC
loop and keeps a constant AGC value.
Figure 28:
AGC
Angular Data (0x3FFF)
Figure 29:
Angular Data
Bit 1514131211109876543 2 1 0
Content000 00000000000 0PAR
Name Read/Write Bit Position Description
AGC R/W 5:0 Automatic Gain Control value
Name Read/Write Bit Position Description
Alarm Lo R 13 Alarm flag, which indicates a too weak magnetic field
Alarm Hi R 12 Alarm flag, which indicates a too strong magnetic field
Angle Value R 9:0 Angular value in 10 bit binary code
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AS5050A − Error Monitoring
Alarm Bits
Figure 30:
Alarm Bits
Error Status (0x335A)
For detailed information of the Error Status Register please refer
to “Error Monitoringon page 22.
System Configuration Register 1 (0x3F20)
The gain setting can be configured in system configuration
register 1. This register contains factory settings. To change the
gain setting, read out the register, modify the gain setting and
write the new configuration. The factory settings must not be
changed.
Figure 31:
System Configuration Register
The correct operation and communication of the AS5050A is
ensured by several error flags. Every read access is supported
by a communication error flag (EF) to indicate a transmission
error in a previous host transmission.
For additional information on the Error Status, please refer to
the application note AN5000_ErrorMonitoring.
Alarm Hi Alarm Lo Description
00
AGC level is higher than the minimum value and lower than the maximum
value.
0 1 AGC level is higher than the maximum level. The magnetic field is too weak.
1 0 AGC level is lower than the minimum level. The magnetic field is too strong.
11
Indicates if a major system error has occurred during the last READ ANGLE
command or if the WOW flag is active. During active WOW a READ ANGLE
command must not be sent. Error flags can be read out with the
error status register.
Name Read/Write Bit Position Description
Resolution R 13:12 01 indicates 10 bit resolution
Chip ID R 11:9 Silicon version 010
Factory Setting R/W 8:5 Don't change
Gain R/W 4:3 Sets gain setting
Factory Setting R/W 2:0 Don't change
Error Monitoring
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AS5050A − Error Monitoring
Error Status Register
Figure 32:
Error Status Register and Description
Bit Type Description
Error Status DSP
13 Reserved
12 FIELD_ALARM_LO AGC level is equal or even higher than the maximum level. Magnetic field is
too weak.
11 FIELD_ALARM_HI AGC level is equal or even lower than the minimum level. Magnetic field is too
strong.
10 RANGE
The RANGE flag signals that the Hall bias circuit has reached the head room
limit. This might occur at the combination of low supply voltage, high
temperature and low magnetic field. In this case, manually reducing the AGC
setting (Figure 28) can be used to recover a valid Hall biasing condition.
9CORDICOV
The CORDIC calculates the angle. An error occurs when the input signals of the
CORDIC are too large. The internal algorithm fails.
8ADCOV
The ADCOV bit occurs if the magnetic input field strength is too large for at
least one Hall element. This can be the case if the magnet is displaced. Second
reason could be that the offset compensation after power up is not finished
yet. If this happens some dummy READ ANGLE commands may be sent to
settle the offset loop.
Error Status System
7Reserved
6Reserved
5Reserved
4WOW
When a READ ANGLE command is in progress, the WOW flag is set to 1. At the
end of the measurement the WOW flag is cleared to 0. Only in case of
deadlock the WOW flag is stuck high; in which case a MASTER RESET must be
sent to clear the deadlock.
Error Status SPI
3Reserved
2 ADDMON Set to high when non existing address is used.
1 CLKMON Set to high when the amount of clock cycles is not correct.
0PARITY
Set to high when the transmitted parity bit does not match to calculated
parity bit.
PIN #1 ID \ ‘ x m DAmM A OR a) L j ,15 mm W A e L EVEN/ODD TERMINAL SIDE TERM‘NAL TIP DETAIL B \ CENTER 0: THE HALL ELEMENTS FA; "‘ M ” SEATING PLANE A ”A w a T m 1 ‘ £1 (mum, E D2 WW ‘3 "N 15 PINmID U U \ U U // ‘2 D ‘ L 1 / 7 ‘ E ¥7+i C ‘ D ' ‘ C / ‘ C 4 ‘ SEE DEYNLB D m l D D (DATMM 8p 8 ‘ 5 m« y * km mun
Page 24 ams Datasheet
Document Feedback [v2-06] 2014-Oct-14
AS5050A − Package Drawings & Markings
The device is available in a 16-pin QFN (4x4x0.9 mm) package.
The axis of the magnet must be aligned over the center of the
package.
Figure 33:
Package FN – Dual Flat No-Lead Packaging Configuration
Note(s) and/or Footnote(s):
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1
represents terminal full back from package edge up to 0.15mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
6. N is the total number of terminals.
Package Drawings & Markings
Symbol Min Nom Max
A 0.80 0.90 1.00
A1 0 0.02 0.05
A3 0.20 REF
L 0.35 0.40 0.45
L1 0 - 0.15
b 0.25 0.30 0.35
D4.00 BSC
E4.00 BSC
e0.65 BSC
D2 2.60 2.70 2.80
E2 2.60 2.70 2.80
aaa - 0.15 -
bbb - 0.10 -
ccc - 0.10 -
ddd - 0.05 -
eee - 0.08 -
fff - 0.10 -
N16
AS5050A @
YYWWXZZ
Green
RoHS
W z m 15H .m m .. Ii ‘1 baa 1: znznlsn , 2‘? M ime C/L aaeamnsa t 0357mm
ams Datasheet Page 25
[v2-06] 2014-Oct-14 Document Feedback
AS5050A − Package Drawings & Markings
Figure 34:
Marking: YYWWXZZ
Figure 35:
Vertical Cross Section of QFN 16-pin 4x4x0.85 mm package
Note(s) and/or Footnote(s):
1. All dimensions in mm.
2. Die thickness 0.254 ± 0.013
3. Adhesive thickness 0.010 ± 10, +0.01, -0.0025
4. Lead frame thickness 0.203 typ.
YY WW XZZ
Year (i.e. 04 for 2004) Week Assembly plant identifier Assembly traceability code
Page 26 ams Datasheet
Document Feedback [v2-06] 2014-Oct-14
AS5050A − Ordering & Contact Information
Figure 36:
Ordering Information
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering Code Package Marking Delivery Form Delivery Quantity
AS5050A-BQFT 16-pin QFN AS5050A 13" Tape & Reel in dry pack 6000
AS5050A-BQFM 16-pin QFN AS5050A 7" Tape & Reel in dry pack 500
Ordering & Contact Information
ams Datasheet Page 27
[v2-06] 2014-Oct-14 Document Feedback
AS5050A − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
Page 28 ams Datasheet
Document Feedback [v2-06] 2014-Oct-14
AS5050A − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
ams Datasheet Page 29
[v2-06] 2014-Oct-14 Document Feedback
AS5050A − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
Page 30 ams Datasheet
Document Feedback [v2-06] 2014-Oct-14
AS5050A − Revision Information
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Changes from 2-05 (2014-Sep-24) to current revision 2-06 (2014-Oct-14) Page
Updated Figure 22 19
Updated Figure 23 19
Updated Figure 29 21
Updated figure 30 22
Revision Information
ams Datasheet Page 31
[v2-06] 2014-Oct-14 Document Feedback
AS5050A − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
5Absolute Maximum Ratings
6 Electrical Characteristics
6 Operating Conditions
6 System Parameters
7 DC/AC Characteristics
8 Detailed Description
8 Noise Performance
9 Typical Application
10 Power Supply Filter
10 Reading an Angle
10 Reducing the Angle Jitter
10 Operating Modes
11 Daisy Chain
12 SPI Interface
12 SPI Timing
13 SPI Wire Mode Selection
14 SPI Transaction
14 SPI Command Frame
15 SPI Read Data Frame
16 SPI Write Data Frame
17 SPI Connection to the microcontroller
18 Daisy Chain, 4 Wire
19 Registers
19 POR OFF (0x3F22)
19 Software Reset (0x3C00)
20 Master Reset (0x33A5)
20 Clear Error Flag (0x3380)
21 No Operation (0x0000)
21 AGC – Automatic Gain Control (0x3FF8)
21 Angular Data (0x3FFF)
22 Alarm Bits
22 Error Status (0x335A)
22 System Configuration Register 1 (0x3F20)
22 Error Monitoring
23 Error Status Register
24 Package Drawings & Markings
26 Ordering & Contact Information
27 RoHS Compliant & ams Green Statement
28 Copyrights & Disclaimer
29 Document Status
30 Revision Information
Content Guide

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