STM8L051F3 Datasheet by STMicroelectronics

‘ ’l hie.ougmenfed TSSOPZO (6 4x4 4 mm 0(155 mis wmlh)

This is information on a product in full production.

September 2018 DS9178 Rev 4 1/96

STM8L051F3

8-bit ultra-low-power MCU, 8-Kbyte Flash memory,

256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC

Datasheet - production data

Features

•Operating conditions

– Operating power supply: 1.8 V to 3.6 V

Temperature range: −40 °C to 85 °C

•Low-power features

– 5 low-power modes: Wait, Low-power run

(5.1 µA), Low-power wait (3 µA), Active-

halt with RTC (1.3 µA), Halt (350 nA)

– Ultra-low leakage per I/O: 50 nA

– Fast wakeup from Halt: 5 µs

•Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

•Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds

– Ultra-low power POR/PDR

– Programmable voltage detector (PVD)

•Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

•Low-power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Auto-wakeup from Halt w/ periodic interrupt

•Memories

– 8 Kbytes of Flash program memory and

256 bytes of data EEPROM with ECC

– Flexible write and read protection modes

– 1 Kbyte of RAM

•DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

•12-bit ADC up to 1 Msps/10 channels

– Internal reference voltage

•Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 8-bit timer with 7-bit prescaler

– 2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

•Communication interfaces

– Synchronous serial interface (SPI)

– Fast I2C 400 kHz SMBus and PMBus

–USART

•Up to 18 I/Os, all mappable on interrupt vectors

•Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

TSSOP20 ( 6.4x4.4 mm or 169 mils width)

www.st.com

Contents STM8L051F3

2/96 DS9178 Rev 4

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 System configuration controller and routing interface . . . . . . . . . . . . . . . 19

3.10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.10.1 16-bit general purpose timers (TIM2, TIM3) . . . . . . . . . . . . . . . . . . . . . 19

3.10.2 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DS9178 Rev 4 3/96

STM8L051F3 Contents

3.15 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 49

8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3.9 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.10 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Contents STM8L051F3

4/96 DS9178 Rev 4

9.3 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

DS9178 Rev 4 5/96

STM8L051F3 List of tables

List of tables

Table 1. STM8L051F3 features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 4. STM8L051F3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 19. Total current consumption and timing in Low power run mode

at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 56

Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 57

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 57

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 58

Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 70

Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 42. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 43. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 44. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 45. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 46. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 47. RAIN max for fADC = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

List of tables STM8L051F3

6/96 DS9178 Rev 4

Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 52. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 53. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

DS9178 Rev 4 7/96

STM8L051F3 List of figures

List of figures

Figure 1. STM8L051F3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. STM8L051F3 clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM8L051F3 20-pin TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 7. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 12. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 14. Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 15. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 18. Typical pull-up resistance RPU vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19. Typical pull-up current Ipu vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 26. Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 27. Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 28. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 29. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 30. SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 31. SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 32. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 33. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 35. Maximum dynamic current consumption on VREF+ supply pin during ADC

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 84

Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 85

Figure 38. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 39. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 40. Device marking for TSSOP20 – 20-lead thin shrink small outline,

6.5 x 4.4 mm, 0.65 mm pitch example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 41. Low density value line STM8L051F3 ordering information scheme . . . . . . . . . . . . . . . . . . 93

Introduction STM8L051F3

8/96 DS9178 Rev 4

1 Introduction

This document describes the features, pinout, mechanical data and ordering information for

the low density STM8L051F3 microcontroller with 8-Kbyte Flash memory density.

For further details on the whole STMicroelectronics low density family please refer to

Section 2.2: Ultra-low-power continuum.

For detailed information on device operation and registers, refer to the STM8L050J3,

STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162,

STM8AL31, STM8AL3L lines reference manual (RM0031).

For information on to the Flash program memory and data EEPROM, refer to the How to

program STM8L and STM8AL Flash program memory and data EEPROM programming

manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

The low density value line devices, including STM8L051F3, provide the following benefits:

•Integrated system

– 8 Kbytes of low-density embedded Flash program memory

– 256 bytes of data EEPROM

– 1 Kbyte of RAM

– Internal high-speed and low-power low speed RC

– Embedded reset

•Ultra-low-power consumption

– 1 µA in Active-halt mode

– Clock gated system and optimized power management

– Capability to execute from RAM for Low-power wait mode and Low-power run

mode

•Advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency

– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access

•Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals

– Wide choice of development tools

These features make STM8L051F3 suitable for a wide range of consumer and mass market

applications.

Refer to Table 1: STM8L051F3 features and peripheral counts and Section 3: Functional

overview for an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the block diagram of the low density STM8L051F3 device.

DS9178 Rev 4 9/96

STM8L051F3 Description

2 Description

STM8L051F3 is member of the STM8L ultra-low-power 8-bit family.

STM8L051F3 features an enhanced STM8 CPU core providing increased processing power

(up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with

improved code density, a 24-bit linear addressing space and an optimized architecture for

low-power operations.

The STM8L051F3 MCU includes an integrated debug module with a hardware interface

(SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash

programming. It features an embedded data EEPROM and low-power, low-voltage, single-

supply program Flash memory.

The device incorporates an extensive range of enhanced I/Os and peripherals, a 12-bit

ADC, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard

communication interfaces such as an SPI, an I2C interface, and one USART.

The modular design of the peripheral set allows this device to have the same peripherals

that can be found in different ST microcontroller families including 32-bit families. This

makes any transition to a different family very easy, supported also by the use of a common

set of development tools.

STM8L051F3 as all the value line STM8L ultra-low-power products are based on the same

architecture with the same memory mapping and a coherent pinout.

Description STM8L051F3

10/96 DS9178 Rev 4

2.1 Device overview

Table 1. STM8L051F3 features and peripheral counts

Features STM8L051F3

Flash (Kbytes) 8

Data EEPROM (Bytes) 256

RAM (Kbytes) 1

Timers

Basic 1

(8-bit)

General

purpose

(16-bit)

Communicati

on interfaces

SPI 1

I2C 1

USART 1

GPIOs 18 (1)

1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the

NRST/PA1 pin as general purpose output only (PA1).

12-bit synchronized ADC

(number of channels)

(10)

Others

RTC, window watchdog, independent watchdog,

16-MHz and 32-kHz internal RC,

1- to 16-MHz and 32-kHz external oscillator

CPU frequency 16 MHz

Operating voltage 1.8 to 3.6 V

Operating temperature − 40 to +85 °C

Package TSSOP20

DS9178 Rev 4 11/96

STM8L051F3 Description

2.2 Ultra-low-power continuum

STM8L051F3 is part of STM8’s ultra-low-power value line on which all the devices are pin-

to-pin, software and feature compatible. Besides the full compatibility within the STM8L

family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy

which also includes the STM8L001xx, STM8L101xx and STM32L15xxx devices. The

STM8L and STM32L families allow a continuum of performance, peripherals, system

architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 STM8L051F3 is pin-to-pin compatible with STM8L101xx devices.

2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.

Please refer to STM32L15x documentation for more information on these devices.

Performance

All the STMicroelectronics ultra-low-power families incorporate highly energy-efficient cores

with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L

families and ARM® 32-bit Cortex®-M3 core for STM32L family. In addition specific care for

the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

The STM8L05xxx, STM8L15xxx and STM32L15xxx devices share identical peripherals

which ensure a very easy migration from one family to another:

•Analog peripheral: ADC1

•Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a

common architecture:

•Same power supply range from 1.8 to 3.6 V

•Architecture optimized to reach ultra-low consumption both in low-power modes and

Run mode

•Fast startup strategy from low-power modes

•Flexible system clock

•Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on

reset, power-down reset, brownout reset and programmable voltage detector.

Features

ST ultra-low-power continuum also lies in feature compatibility:

•More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

•Memory density ranging from 4 to 128 Kbytes

Functional overview STM8L051F3

12/96 DS9178 Rev 4

3 Functional overview

Figure 1. STM8L051F3 block diagram

1. Legend:

ADC: Analog-to-digital converter

BOR: Brownout reset

DMA: Direct memory access

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent watchdog

POR/PDR: Power-on reset / power-down reset

RTC: Real-time clock

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

WWDG: Window watchdog

MS30321V2

Clock

controller

and CSS Clocks

A ddress , control and data buses

8-Kbyte

1-Kbyte RAM

to core and

peripherals

IWDG

(38 kHz clock)

Port A

Port B

Port C

Power

VOLT. REG.

WWDG

256-byte

Port D

Beeper

RTC

memoryProgram

Data EEPROM

@V DD

VDD18 VDD =1.8 V

VSS

SWIM

SCL, SDA,

SPI1_MOSI, SPI1_MISO,

SPI1_SCK, SPI1_NSS

USART1_RX, USART1_TX,

USART1_CK

ADC1_INx

VDDA, VSSA

SMB

@VDDA /V

SSA

12-bit ADC1

VDDREF

3.6 V

NRST

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

BEEP

ALARM,

TAMP1/2/3

POR/PDR

OSC_IN,

OSC_OUT

OSC32_IN,

OSC32_OUT

BOR

PVD PVD_IN

RESET

DMA1 (4 channels)

2 channels

Internal reference

voltage

VREFINT out

IR_TIM

1-16 MHz oscillator

16 MHz internal RC

32 kHz oscillator

STM8 Core

16-bit Timer 2

38 kHz internal RC

Interrupt controller

16-bit Timer 3

Debug module

(SWIM)

8-bit Timer 4

Infrared interface

SPI1

I²C1

USART1

VSSREF

(2)

DS9178 Rev 4 13/96

STM8L051F3 Functional overview

3.1 Low-power modes

STM8L051F3 as well as all the low density value line STM8L05xxx devices support five low-

power modes to achieve the best compromise between low power consumption, short

startup time and available wakeup sources:

•Wait mode: The CPU clock is stopped, but selected peripherals keep running. An

internal or external interrupt or a Reset can be used to exit the microcontroller from

Wait mode (WFE or WFI mode).

•Low-power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data

EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.

The microcontroller enters Low-power run mode by software and can exit from this

mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

•Low-power wait mode: This mode is entered when executing a Wait for event in Low-

power run mode. It is similar to Low-power run mode except that the CPU clock is

stopped. The wakeup from this mode is triggered by a Reset or by an internal or

external event (peripheral event generated by the timers, serial interfaces, DMA

controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the

system goes back to Low-power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

•Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

•Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. The wakeup is triggered by an external interrupt or

reset. A few peripherals have also a wakeup from Halt capability. Switching off the

internal reference voltage reduces power consumption. Through software configuration

it is also possible to wake up the device without waiting for the internal reference

voltage wakeup time to have a fast wakeup time of 5 µs.

Functional overview STM8L051F3

14/96 DS9178 Rev 4

3.2 Central processing unit STM8

The central processing unit represents the core of the microcontroller; it executes code and

controls the peripherals.

3.2.1 Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard

architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

•Harvard architecture

•3-stage pipeline

•32-bit wide program memory bus - single cycle fetching most instructions

•X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

•8-bit accumulator

•24-bit program counter - 16-Mbyte linear memory space

•16-bit stack pointer - access to a 64-Kbyte level stack

•8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

•20 addressing modes

•Indexed indirect addressing mode for lookup tables located anywhere in the address

space

•Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

•80 instructions with 2-byte average instruction size

•Standard data movement and logic/arithmetic functions

•8-bit by 8-bit multiplication

•16-bit by 8-bit and 16-bit by 16-bit division

•Bit manipulation

•Data transfer between stack and accumulator (push/pop) with direct stack access

•Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2 Interrupt controller

STM8L051F3 and all the low density value line STM8L05xxx feature a nested vectored

interrupt controller:

•Nested interrupts with 3 software priority levels

•32 interrupt vectors with hardware priority

•Up to 17 external interrupt sources on 11 vectors

•Trap and reset interrupts

DS9178 Rev 4 15/96

STM8L051F3 Functional overview

3.3 Reset and supply management

The power supplies requirements must be defined in order to have a correct microcontroller

operation. The reset and supply management controls the microcontroller operation under

defined conditions.

3.3.1 Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power

supply pins must be connected as follows:

•VSS1; VDD1 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.

Provided externally through VDD1 pins, the corresponding ground pin is VSS1.

•VSSA; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and

VSSA must be connected to VDD1 and VSS1, respectively.

•VSS2; VDD2 = 1.8 to 3.6 V: external power supplies for I/Os. VDD2 and VSS2 must be

connected to VDD1 and VSS1, respectively.

•VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be

providedexternally through VREF+ and VREF- pin.

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates

between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from

1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,

either to confirm or modify default thresholds, or to disable BOR permanently.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Halt mode, it is possible to automatically switch off the

internal reference voltage (and consequently the BOR) in Halt mode. The device remains in

reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for

any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when

VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

STM8L051F3 as all the low density value line STM8L05xxx embeds an internal voltage

regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

•Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes.

•Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and

Low-power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR

to the LPVR in order to reduce current consumption.

Functional overview STM8L051F3

16/96 DS9178 Rev 4

3.4 Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators

to the core and the peripherals. It also manages clock gating for low-power modes and

ensures clock robustness.

Features

•Clock prescaler: to get the best compromise between speed and current consumption

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler.

•Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

•Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

•System clock sources: four different clock sources can be used to drive the system

clock:

– 1-16 MHz High speed external crystal (HSE)

– 16 MHz High speed internal RC oscillator (HSI)

– 32.768 Low speed external crystal (LSE)

– 38 kHz Low speed internal RC (LSI)

•RTC clock sources: the above four sources can be chosen to clock the RTC whatever

the system clock.

•Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

•Clock security system (CSS): This feature can be enabled by software. If a HSE

clock failure occurs, it is automatically switched to HSI.

•Configurable main clock output (CCO): This outputs an external clock for use by the

application.

DS9178 Rev 4 17/96

STM8L051F3 Functional overview

Figure 2. STM8L051F3 clock tree diagram

1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE

bypass). Refer to Section HSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8

MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).

2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE

bypass). Refer to Section LSE clock in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8

MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).

OSC_OUT

OSC_IN

HSE

HSI

LSI

LSE

LSI

HSE OSC

1-16 MHz

HSI RC

1-16 MHz

LSI RC

38 kHz

LSE OSC

32.768 kHz

OSC32_OUT

OSC32_IN

CCO

Configurable

clock output

/1;2;4;8;16;32;64

prescaler

CCO

HSE

HSI

LSI

LSE

/1;2;4;8;16;32;64

prescaler

SYSCLK

SYSCLK to core and

memory

PCLK to

peripherals

Peripheral

Clock

CLKBEEPSEL[1:0]

IWDGCLK

BEEPCLK

RTCCLK

enable (13 bits)

RTCSEL[3:0]

RTC

/1;2;4;8;16;32;64

prescaler

BEEP

IWDG

RTC

MS18281V2

SWIM[3:0]

CCOSEL[3:0]

Functional overview STM8L051F3

18/96 DS9178 Rev 4

3.5 Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,

year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31

day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from

Halt capability.

•Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach

36 hours

•Periodic alarms based on the calendar can also be generated from every second to

every year

3.6 Memories

STM8L051F3 as all the low density value line STM8L05xxx devices have the following main

features:

•Up to 1 Kbyte of RAM

•The non-volatile memory is divided into three arrays:

– 8 Kbytes of low-density embedded Flash program memory

– 256 bytes of Data EEPROM

– Option bytes

The EEPROM embeds the error correction code (ECC) feature.

The option byte protects part of the Flash program memory from write and readout piracy.

3.7 DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and

peripherals-from/to-memory transfer capability. The 4 channels are shared between the

following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, and the three timers.

3.8 Analog-to-digital converter

•12-bit analog-to-digital converter (ADC1) with 10 channels (no fast channel) and

internal reference voltage

•Conversion time down to 1 µs with fSYSCLK= 16 MHz

•Programmable resolution

•Programmable sampling time

•Single and continuous mode of conversion

•Scan capability: automatic conversion performed on a selected group of analog inputs

•Analog watchdog

•Triggered by timer

Note: ADC1 can be served by DMA1.

DS9178 Rev 4 19/96

STM8L051F3 Functional overview

3.9 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate

functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface controls the routing of internal analog signals to ADC1

and the internal reference voltage VREFINT.

3.10 Timers

STM8L051F3 contains two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit

basic timer (TIM4).

All the timers can be served by DMA1.

Table 2 compares the features of the advanced control, general-purpose and basic timers.

3.10.1 16-bit general purpose timers (TIM2, TIM3)

•16-bit autoreload (AR) up/down-counter

•7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

•2 individually configurable capture/compare channels

•PWM mode

•Interrupt capability on various events (capture, compare, overflow, break, trigger)

•Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.10.2 8-bit basic timer (TIM4)

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable

prescaler. It can be used for timebase generation with interrupt generation on timer

overflow.

3.11 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

Table 2. Timer feature comparison

Timer Counter

resolution

Counter

type Prescaler factor

DMA1

request

generation

Capture/compare

channels

Complementary

outputs

TIM2

16-bit up/down Any power of 2

from 1 to 128

Yes

None

TIM3 2

TIM4 8-bit up Any power of 2

from 1 to 32768 0

Functional overview STM8L051F3

20/96 DS9178 Rev 4

3.11.1 Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

3.11.2 Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor

malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a

CPU clock failure.

3.12 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in

the range of 1, 2 or 4 kHz.

3.13 Communication interfaces

This section describes the three communication interfaces of STM8L050J3: SPI, I2C and

USART.

3.13.1 SPI

The serial peripheral interfaces (SPI1) provide half/ full duplex synchronous serial

communication with external devices.

•Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave

•Full duplex synchronous transfers

•Simplex synchronous transfers on 2 lines with a possible bidirectional data line

•Master or slave operation - selectable by hardware or software

•Hardware CRC calculation

•Slave/master selection input pin

Note: SPI1 can be served by the DMA1 Controller.

3.13.2 I2C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I2C bus-

specific sequencing, protocol, arbitration and timing.

•Master, slave and multi-master capability

•Standard mode up to 100 kHz and fast speed modes up to 400 kHz

•7-bit and 10-bit addressing modes

•SMBus 2.0 and PMBus support

•Hardware CRC calculation

Note: I2C1 can be served by the DMA1 Controller.

DS9178 Rev 4 21/96

STM8L051F3 Functional overview

3.13.3 USART

The USART interface (USART1) allows full duplex, asynchronous communications with

external devices requiring an industry standard NRZ asynchronous serial data format. It

offers a very wide range of baud rates.

•1 Mbit/s full duplex SCI

•SPI1 emulation

•High precision baud rate generator

•Smartcard emulation

•IrDA SIR encoder decoder

•Single wire half duplex mode

Note: USART1 can be served by the DMA1 Controller.

3.14 Infrared (IR) interface

The low density STM8L05xxx devices contain an infrared interface which can be used with

an IR LED for remote control functions. Two timer output compare channels are used to

generate the infrared remote control signals.

3.15 Development support

Development tools

Development tools for the STM8 microcontrollers include:

•The STice emulation system offering tracing and code profiling

•The STVD high-level language debugger including C compiler, assembler and

integrated development environment

•The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time

in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory

programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured

emulator. Beside memory and peripherals, CPU operation can also be monitored in real-

time by means of shadow registers.

If the initial delay is not acceptable for the application there is the option that the firmware

reenables the SWIM pin functionality under specific conditions such as during firmware

startup or during application run. Once that this procedure is done, the SWIM interface can

be used for device debug/programming.

Functional overview STM8L051F3

22/96 DS9178 Rev 4

Bootloader

STM8L051F3 features a built-in bootloader. See STM8 bootloader user manual (UM0560).

The bootloader is used to download application software into the device memories,

including RAM, program and data memory, using standard serial interfaces. It is a

complementary solution to programming via the SWIM debugging interface.

3:333:33]: :EDDEEEEEE

DS9178 Rev 4 23/96

STM8L051F3 Pin description

4 Pin description

Figure 3. STM8L051F3 20-pin TSSOP20 package pinout

Table 3. Legend/abbreviation for Table 4

Type I= input, O = output, S = power supply

Level Output HS = high sink/source (20 mA)

Input FT - five volt tolerant

Port and control

configuration

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Reset state

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase

(i.e. “under reset”) and after internal reset release (i.e. at reset state).

PA3

PA2

VSS/VSSA/VREF-

NRST / PA1

PC0

PC1

PB7

PB6

PB1

PB2

PB3

PB4

PB5

VDD/VDDA/VREF+

PC4

MS18280V1

PB0

PD0

PA0

PC6

PC5

Pin description STM8L051F3

24/96 DS9178 Rev 4

Table 4. STM8L051F3 pin description

n°

Pin name

Type

I/O level

Input Output

Main function

(after reset)

Default alternate function

TSSOP20

floating

wpu

Ext. interrupt

High sink/source

4 NRST/PA1(1) I/O - - X-HS- XReset PA1

5PA2/OSC_IN/[USART_TX](2)/

[SPI_MISO] (2) I/O - XXXHSXX

Port

HSE oscillator input / [USART

transmit] / [SPI master in- slave out]

6PA3/OSC_OUT/[USART_RX](2)

/[SPI_MOSI](2) I/O - XXXHSXX

Port

HSE oscillator output / [USART

receive]/ [SPI master out/slave in]

10 PB0(3)/TIM2_CH1/ADC1_IN18 I/O - XXXHSXX

Port

B0 Timer 2 - channel 1 / ADC1_IN18

11 PB1/TIM3_CH1/ADC1_IN17 I/O - XXXHSXX

Port

B1 Timer 3 - channel 1 / ADC1_IN17

12 PB2/ TIM2_CH2/ ADC1_IN16 I/O - XXXHSXX

Port

B2 Timer 2 - channel 2 ADC1_IN16

13 PB3/TIM2_ETR/

ADC1_IN15/RTC_ALARM I/O - XXXHSXX

Port

Timer 2 - external trigger /

ADC1_IN15 / RTC_ALARM

14 PB4(3)/SPI1_NSS/ADC1_IN14 I/O - XXXHSXX

Port

SPI master/slave select /

ADC1_IN14

15 PB5/SPI_SCK/

/ADC1_IN13 I/O - XXXHSXX

Port

B5 [SPI clock] / ADC1_IN13

16 PB6/SPI1_MOSI/

ADC1_IN12 I/O - XXXHSXX

Port

SPI master out/

slave in / ADC1_IN12

17 PB7/SPI1_MISO/ADC1_IN11 I/O - XXXHSXX

Port

SPI1 master in- slave out/

ADC1_IN11

18 PC0/I2C_SDA I/O FT X-X-T

(4) Port

C0 I2C data

19 PC1/I2C_SCL I/O FT X-X-T

(3) Port

C1 I2C clock

20 PC4/USART_CK/

I2C_SMB/CCO/ADC1_IN4 I/O - XXXHSXX

Port

USART synchronous clock /

I2C1_SMB / Configurable clock

output / ADC1_IN4

1PC5/OSC32_IN /[SPI1_NSS](2)/

[USART_TX]/[TIM2_CH1] I/O - XXXHSXX

Port

LSE oscillator input / [SPI

master/slave select] / [USART

transmit]/Timer 2 -channel 1

DS9178 Rev 4 25/96

STM8L051F3 Pin description

Note: 1 The slope control of all GPIO pins, except true open drain pins, can be programmed. By

default, the slope control is limited to 2 MHz.

4.1 System configuration options

As shown in Table 4: STM8L051F3 pin description, some alternate functions can be

remapped on different I/O ports by programming one of the two remapping registers

described in the “Routing interface (RI) and system configuration controller” section in the

STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152,

STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).

2PC6/OSC32_OUT/[SPI_SCK](2)

/[USART_RX]/[TIM2_CH2] I/O - XXXHSXX

Port

LSE oscillator output / [SPI clock] /

[USART receive]/

Timer 2 -channel 2

9PD0/TIM3_CH2/[ADC1_TRIG](2

)/ADC1_IN22 I/O - XXXHSXX

Port

Timer 3 - channel 2 /

[ADC1_Trigger] / ADC1_IN22

DD / VDDA / VREF+ S-

Digital supply voltage /

ADC1 positive voltage reference

SS / VREF- / VSSA -Ground voltage / ADC1 negative voltage

reference / Analog ground voltage

3PA0(5)/[USART_CK](2)/

SWIM/BEEP/IR_TIM (6) I/O - X XXHS

(6) XX

Port

[USART1 synchronous clock](2) /

SWIM input and output /

Beep output / Infrared timer output

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be

configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1

pin as general purpose output in the STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L

MCU lines reference manual (RM0031).

2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a

duplication of the function).

3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not

implemented).

5. The PA0 pin is in input pull-up during the reset phase and after reset release.

6. High Sink LED driver capability available on PA0.

Table 4. STM8L051F3 pin description (continued)

n°

Pin name

Type

I/O level

Input Output

Main function

(after reset)

Default alternate function

TSSOP20

floating

wpu

Ext. interrupt

High sink/source

Memory and register map STM8L051F3

26/96 DS9178 Rev 4

5 Memory and register map

The following sections describe the mapping of the device’s memory and peripherals.

5.1 Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end

GPIO and peripheral registers

0x00 0000

Low densit y

(8 Kbyt es)

Reset and interrupt vectors

0x0 0 10FF

RAM

0x0 0 03FF

( Kbyte)

(512 bytes)

0x00 1100

Data EEPROM

0x00 4800

0x0 0 487F

0x00 4880

0x00 7FFF

0x00 8000

0x00 9FFF

0x0 0 100 0

0x0 0 47FF

0x00 7EFF

0x00 8100

0 x00 80 FF

0 x00 7F0 0

Reserved

in cl ud in g

Stack

(256 Bytes)

Option bytes

0x00 4FFF

0x00 5000

0x0 0 5457

0x00 5458

Re s er v ed

0x00 5FFF

Boot ROM

0x00 6000

0x0 0 67FF (2 Kbytes)

0x00 6800

Re s er v ed

CPU/SWIM/Debug/ITC

Registers

Flash program memory

Re s er v ed

MS18274V3

Up to 1

Reserved

0x0 0 040 0

0x0 0 1FFF

Reserved

0x00 5000

0x00 501E

0x00 5050

0x00 5055

0x00 5070

0x00 509D

0x00 50A0

0x00 50A6

0x00 50AA

0x00 50A9

0x00 50B0

0x00 50B2

0x00 50B4

0x00 50C0

0x00 50D1

0x00 50D3

0x00 50D5

0x00 50E0

0x00 50E3

0x00 50F0

0x00 50F4

0x00 5040

0x00 5191

0x00 5200

0x00 5208

0x00 5210

0x00 521F

0x00 5230

0x00 523B

0x00 5250

0x00 5267

0x00 5280

0x00 5297

0x00 52E0

0x00 52EA

0x00 52FF

0x00 5317

0x00 5340

0x00 53C8

0x00 5430

0x00 5440

0x00 5450

0x00 5457

Reserved

GPIO ports

Flash

Reserved

DMA1

SYSCFG

ITC-EXT1

WFE

RST

PWR

CLK

WWDG

ITC-EXT1

Reserved

IWDG

BEEP

RTC

SPI1

I2C1

USART1

TIM2

TIM3

Reserved

TIM4

IRTIM

ADC1

DS9178 Rev 4 27/96

STM8L051F3 Memory and register map

address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware

registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

5.2 Register map

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 1 Kbyte 0x00 0000 0x00 03FF

Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF

Table 6. I/O port hardware register map

Address Block Register label Register name Reset

status

0x00 5000

Port A

PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x01

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

Port B

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

Port C

PC_ODR Port C data output latch register 0x00

0x00 500B PB_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

Port D

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

0x00 501D

Reserved area (0 bytes)

Memory and register map STM8L051F3

28/96 DS9178 Rev 4

Table 7. General hardware register map

Address Block Register label Register name Reset

status

0x00 502E

0x00 5049

Reserved area (44 bytes)

0x00 5050

Flash

FLASH_CR1 Flash control register 1 0x00

0x00 5051 FLASH_CR2 Flash control register 2 0x00

0x00 5052 FLASH _PUKR Flash program memory unprotection key register 0x00

0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00

0x00 5054 FLASH _IAPSR Flash in-application programming status register 0x00

0x00 5055

0x00 506F

Reserved area (27 bytes)

0x00 5070

DMA1

DMA1_GCSR DMA1 global configuration & status register 0xFC

0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00

0x00 5072 to

0x00 5074

Reserved area (3

bytes)

0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00

0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00

0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register

(channel 0) 0x00

0x00 5078 DMA1_C0PARH DMA1 peripheral address high register

(channel 0) 0x52

0x00 5079 DMA1_C0PARL DMA1 peripheral address low register

(channel 0) 0x00

0x00 507A Reserved area (1 byte)

0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register

(channel 0) 0x00

0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register

(channel 0) 0x00

DS9178 Rev 4 29/96

STM8L051F3 Memory and register map

0x00 507D to

0x00 507E

DMA1

Reserved area (2 bytes)

0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00

0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00

0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register

(channel 1) 0x00

0x00 5082 DMA1_C1PARH DMA1 peripheral address high register

(channel 1) 0x52

0x00 5083 DMA1_C1PARL DMA1 peripheral address low register

(channel 1) 0x00

0x00 5084 Reserved area (1 byte)

0x00 5085 DMA1_C1M0ARH DMA1 memory 0 address high register

(channel 1) 0x00

0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register

(channel 1) 0x00

0x00 5087

0x00 5088 Reserved area (2 bytes)

0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00

0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00

0x00 508B DMA1_C2NDTR DMA1 number of data to transfer register

(channel 2) 0x00

0x00 508C DMA1_C2PARH DMA1 peripheral address high register

(channel 2) 0x52

0x00 508D DMA1_C2PARL DMA1 peripheral address low register

(channel 2) 0x00

0x00 508E Reserved area (1 byte)

0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register

(channel 2) 0x00

0x00 5090 DMA1_C2M0ARL DMA1 memory 0 address low register

(channel 2) 0x00

0x00 5091

0x00 5092 Reserved area (2 bytes)

0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00

0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00

0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register

(channel 3) 0x00

0x00 5096 DMA1_C3PARH_

C3M1ARH

DMA1 peripheral address high register

(channel 3) 0x40

0x00 5097 DMA1_C3PARL_

C3M1ARL

DMA1 peripheral address low register

(channel 3) 0x00

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

Memory and register map STM8L051F3

30/96 DS9178 Rev 4

0x00 5098

DMA1

DMA_C3M0EAR DMA channel 3 memory 0 extended address

0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register

(channel 3) 0x00

0x00 509A DMA1_C3M0ARL DMA1 memory 0 address low register

(channel 3) 0x00

0x00 509B to

0x00 509C Reserved area (3 bytes)

0x00 509D

SYSCFG

SYSCFG_RMPCR3 Remapping register 3 0x00

0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00

0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00

0x00 50A0

ITC - EXTI

EXTI_CR1 External interrupt control register 1 0x00

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00

0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00

0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00

0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00

0x00 50A6

WFE

WFE_CR1 WFE control register 1 0x00

0x00 50A7 WFE_CR2 WFE control register 2 0x00

0x00 50A8 WFE_CR3 WFE control register 3 0x00

0x00 50A9 WFE_CR4 WFE control register 4 0x00

0x00 50AA

ITC - EXTI

EXTI_CR4 External interrupt control register 4 0x00

0x00 50AB EXTI_CONF2 External interrupt port select register 2 0x00

0x00 50A9

0x00 50AF

Reserved area (7 bytes)

0x00 50B0

RST

RST_CR Reset control register 0x00

0x00 50B1 RST_SR Reset status register 0x01

0x00 50B2

PWR

PWR_CSR1 Power control and status register 1 0x00

0x00 50B3 PWR_CSR2 Power control and status register 2 0x00

0x00 50B4

0x00 50BF

Reserved area (12 bytes)

0x00 50C0

CLK

CLK_CKDIVR CLK Clock master divider register 0x03

0x00 50C1 CLK_CRTCR CLK Clock RTC register 0x00(1)

0x00 50C2 CLK_ICKCR CLK Internal clock control register 0x11

0x00 50C3 CLK_PCKENR1 CLK Peripheral clock gating register 1 0x00

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

DS9178 Rev 4 31/96

STM8L051F3 Memory and register map

0x00 50C4

CLK

CLK_PCKENR2 CLK Peripheral clock gating register 2 0x00

0x00 50C5 CLK_CCOR CLK Configurable clock control register 0x00

0x00 50C6 CLK_ECKCR CLK External clock control register 0x00

0x00 50C7 CLK_SCSR CLK System clock status register 0x01

0x00 50C8 CLK_SWR CLK System clock switch register 0x01

0x00 50C9 CLK_SWCR CLK Clock switch control register 0xX0

0x00 50CA CLK_CSSR CLK Clock security system register 0x00

0x00 50CB CLK_CBEEPR CLK Clock BEEP register 0x00

0x00 50CC CLK_HSICALR CLK HSI calibration register 0xXX

0x00 50CD CLK_HSITRIMR CLK HSI clock calibration trimming register 0x00

0x00 50CE CLK_HSIUNLCKR CLK HSI unlock register 0x00

0x00 50CF CLK_REGCSR CLK Main regulator control status register 0bxx11 1

00X

0x00 50D0 CLK_PCKENR3 CLK Peripheral clock gating register 3 0x00

0x00 50D1

0x00 50D2

Reserved area (2 bytes)

0x00 50D3

WWDG

WWDG_CR WWDG control register 0x7F

0x00 50D4 WWDG_WR WWDR window register 0x7F

0x00 50D5

00 50DF

Reserved area (11 bytes)

0x00 50E0

IWDG

IWDG_KR IWDG key register 0x01

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3

0x00 50EF

Reserved area (13 bytes)

0x00 50F0

BEEP

BEEP_CSR1 BEEP control/status register 1 0x00

0x00 50F1

0x00 50F2 Reserved area (2 bytes)

0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F

0x00 50F4

to0x00 513F Reserved area (76 bytes)

0x00 5140

RTC

RTC_TR1 RTC Time register 1 0x00

0x00 5141 RTC_TR2 RTC Time register 2 0x00

0x00 5142 RTC_TR3 RTC Time register 3 0x00

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

Memory and register map STM8L051F3

32/96 DS9178 Rev 4

0x00 5143

RTC

Reserved area (1 byte)

0x00 5144 RTC_DR1 RTC Date register 1 0x01

0x00 5145 RTC_DR2 RTC Date register 2 0x21

0x00 5146 RTC_DR3 RTC Date register 3 0x00

0x00 5147 Reserved area (1 byte)

0x00 5148 RTC_CR1 RTC Control register 1 0x00(1)

0x00 5149 RTC_CR2 RTC Control register 2 0x00(1)

0x00 514A RTC_CR3 RTC Control register 3 0x00(1)

0x00 514B Reserved area (1 byte)

0x00 514C RTC_ISR1 RTC Initialization and status register 1 0x01

0x00 514D RTC_ISR2 RTC Initialization and Status register 2 0x00

0x00 514E

0x00 514F Reserved area (2 bytes)

0x00 5150 RTC_SPRERH RTC Synchronous prescaler register high 0x00(1)

0x00 5151 RTC_SPRERL RTC Synchronous prescaler register low 0xFF(1)

0x00 5152 RTC_APRER RTC Asynchronous prescaler register 0x7F(1)

0x00 5153 Reserved area (1 byte)

0x00 5154 RTC_WUTRH RTC Wakeup timer register high 0xFF(1)

0x00 5155 RTC_WUTRL RTC Wakeup timer register low 0xFF(1)

0x00 5156 Reserved area (1 byte)

0x00 5157 RTC_SSRL RTC Subsecond register low 0x00

0x00 5158 RTC_SSRH RTC Subsecond register high 0x00

0x00 5159 RTC_WPR RTC Write protection register 0x00

0x00 5158 RTC_SSRH RTC Subsecond register high 0x00

0x00 5159 RTC_WPR RTC Write protection register 0x00

0x00 515A RTC_SHIFTRH RTC Shift register high 0x00

0x00 515B RTC_SHIFTRL RTC Shift register low 0x00

0x00 515C RTC_ALRMAR1 RTC Alarm A register 1 0x00(1)

0x00 515D RTC_ALRMAR2 RTC Alarm A register 2 0x00(1)

0x00 515E RTC_ALRMAR3 RTC Alarm A register 3 0x00(1)

0x00 515F RTC_ALRMAR4 RTC Alarm A register 4 0x00(1)

0x00 5160 to

0x00 5163 Reserved area (4 bytes)

0x00 5164 RTC_ALRMASSRH RTC Alarm A subsecond register high 0x00(1)

0x00 5165 RTC_ALRMASSRL RTC Alarm A subsecond register low 0x00(1)

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

DS9178 Rev 4 33/96

STM8L051F3 Memory and register map

0x00 5166

RTC

RTC_ALRMASSMSKR RTC Alarm A masking register 0x00(1)

0x00 5167 to

0x00 5169 Reserved area (3 bytes)

0x00 516A RTC_CALRH RTC Calibration register high 0x00(1)

0x00 516B RTC_CALRL RTC Calibration register low 0x00(1)

0x00 516C RTC_TCR1 RTC Tamper control register 1 0x00(1)

0x00 516D RTC_TCR2 RTC Tamper control register 2 0x00(1)

0x00 516E to

0x00 518A Reserved area (36 bytes)

0x00 5190 CSSLSE_CSR CSS on LSE control and status register 0x00(1)

0x00 519A to

0x00 51FF Reserved area (111 bytes)

0x00 5200

SPI1

SPI1_CR1 SPI1 control register 1 0x00

0x00 5201 SPI1_CR2 SPI1 control register 2 0x00

0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00

0x00 5203 SPI1_SR SPI1 status register 0x02

0x00 5204 SPI1_DR SPI1 data register 0x00

0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07

0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00

0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00

0x00 5208

0x00 520F

Reserved area (8 bytes)

0x00 5210

I2C1

I2C1_CR1 I2C1 control register 1 0x00

0x00 5211 I2C1_CR2 I2C1 control register 2 0x00

0x00 5212 I2C1_FREQR I2C1 frequency register 0x00

0x00 5213 I2C1_OARL I2C1 own address register low 0x00

0x00 5214 I2C1_OARH I2C1 own address register high 0x00

0x00 5215 I2C1_OAR2 I2C1 own address register for dual mode 0x00

0x00 5216 I2C1_DR I2C1 data register 0x00

0x00 5217 I2C1_SR1 I2C1 status register 1 0x00

0x00 5218 I2C1_SR2 I2C1 status register 2 0x00

0x00 5219 I2C1_SR3 I2C1 status register 3 0x0X

0x00 521A I2C1_ITR I2C1 interrupt control register 0x00

0x00 521B I2C1_CCRL I2C1 clock control register low 0x00

0x00 521C I2C1_CCRH I2C1 clock control register high 0x00

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

Memory and register map STM8L051F3

34/96 DS9178 Rev 4

0x00 521D

I2C1

I2C1_TRISER I2C1 TRISE register 0x02

0x00 521E I2C1_PECR I2C1 packet error checking register 0x00

0x00 521F

0x00 522F

Reserved area (17 bytes)

0x00 5230

USART1

USART1_SR USART1 status register 0xC0

0x00 5231 USART1_DR USART1 data register 0xXX

0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00

0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00

0x00 5234 USART1_CR1 USART1 control register 1 0x00

0x00 5235 USART1_CR2 USART1 control register 2 0x00

0x00 5236 USART1_CR3 USART1 control register 3 0x00

0x00 5237 USART1_CR4 USART1 control register 4 0x00

0x00 5238 USART1_CR5 USART1 control register 5 0x00

0x00 5239 USART1_GTR USART1 guard time register 0x00

0x00 523A USART1_PSCR USART1 prescaler register 0x00

0x00 523B

0x00 524F

Reserved area (21 bytes)

0x00 5250

TIM2

TIM2_CR1 TIM2 control register 1 0x00

0x00 5251 TIM2_CR2 TIM2 control register 2 0x00

0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00

0x00 5253 TIM2_ETR TIM2 external trigger register 0x00

0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00

0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5256 TIM2_SR1 TIM2 status register 1 0x00

0x00 5257 TIM2_SR2 TIM2 status register 2 0x00

0x00 5258 TIM2_EGR TIM2 event generation register 0x00

0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

0x00 525C TIM2_CNTRH TIM2 counter high 0x00

0x00 525D TIM2_CNTRL TIM2 counter low 0x00

0x00 525E TIM2_PSCR TIM2 prescaler register 0x00

0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

DS9178 Rev 4 35/96

STM8L051F3 Memory and register map

0x00 5260

TIM2

TIM2_ARRL TIM2 auto-reload register low 0xFF

0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00

0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5265 TIM2_BKR TIM2 break register 0x00

0x00 5266 TIM2_OISR TIM2 output idle state register 0x00

0x00 5267 to

0x00 527F Reserved area (25 bytes)

0x00 5280

TIM3

TIM3_CR1 TIM3 control register 1 0x00

0x00 5281 TIM3_CR2 TIM3 control register 2 0x00

0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00

0x00 5283 TIM3_ETR TIM3 external trigger register 0x00

0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00

0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5286 TIM3_SR1 TIM3 status register 1 0x00

0x00 5287 TIM3_SR2 TIM3 status register 2 0x00

0x00 5288 TIM3_EGR TIM3 event generation register 0x00

0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00

0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00

0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00

0x00 528C TIM3_CNTRH TIM3 counter high 0x00

0x00 528D TIM3_CNTRL TIM3 counter low 0x00

0x00 528E TIM3_PSCR TIM3 prescaler register 0x00

0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF

0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF

0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00

0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00

0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00

0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00

0x00 5295 TIM3_BKR TIM3 break register 0x00

0x00 5296 TIM3_OISR TIM3 output idle state register 0x00

0x00 5297 to

0x00 52DF Reserved area (72 bytes)

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

Memory and register map STM8L051F3

36/96 DS9178 Rev 4

0x00 52E0

TIM4

TIM4_CR1 TIM4 control register 1 0x00

0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00

0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00

0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00

0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00

0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00

0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00

0x00 52E7 TIM4_CNTR TIM4 counter 0x00

0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00

0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00

0x00 52EA

0x00 52FE

Reserved area (21 bytes)

0x00 52FF IRTIM IR_CR Infrared control register 0x00

0x00 5317

0x00 533F

Reserved area (41 bytes)

0x00 5340

ADC1

ADC1_CR1 ADC1 configuration register 1 0x00

0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00

0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F

0x00 5343 ADC1_SR ADC1 status register 0x00

0x00 5344 ADC1_DRH ADC1 data register high 0x00

0x00 5345 ADC1_DRL ADC1 data register low 0x00

0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F

0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF

0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00

0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00

0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00

0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00

0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00

0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00

0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00

0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00

0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00

0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

DS9178 Rev 4 37/96

STM8L051F3 Memory and register map

0x00 53C8 to

0x00 542F Reserved area(104 bytes)

0x00 5430

Reserved area (1 byte) 0x00

0x00 5433 RI_IOIR1 RI I/O input register 1 0xXX

0x00 5434 RI_IOIR2 RI I/O input register 2 0xXX

0x00 5435 RI_IOIR3 RI I/O input register 3 0xXX

0x00 5436 RI_IOCMR1 RI I/O control mode register 1 0x00

0x00 5437 RI_IOCMR2 RI I/O control mode register 2 0x00

0x00 5438 RI_IOCMR3 RI I/O control mode register 3 0x00

0x00 5439 RI_IOSR1 RI I/O switch register 1 0x00

0x00 543A RI_IOSR2 RI I/O switch register 2 0x00

0x00 543B RI_IOSR3 RI I/O switch register 3 0x00

0x00 543C RI_IOGCR RI I/O group control register 0xFF

0x00 543D RI_ASCR1 Analog switch register 1 0x00

0x00 543E RI_ASCR2 RI Analog switch register 2 0x00

0x00 543F RI_RCR RI Resistor control register 0x00

0x00 5440

0x00 544F

Reserved area (16 bytes)

0x00 5450

RI_CR RI I/O control register 0x00

0x00 5451 RI_MASKR1 RI I/O mask register 1 0x00

0x00 5452 RI_MASKR2 RI I/O mask register 2 0x00

0x00 5453 RI_MASKR3 RI I/O mask register 3 0x00

0x00 5454 RI_MASKR4 RI I/O mask register 4 0x00

0x00 5455 RI_IOIR4 RI I/O input register 4 0xXX

0x00 5456 RI_IOCMR4 RI I/O control mode register 4 0x00

0x00 5457 RI_IOSR4 RI I/O switch register 4 0x00

1. These registers are not impacted by a system reset. They are reset at power-on.

Table 7. General hardware register map (continued)

Address Block Register label Register name Reset

status

Memory and register map STM8L051F3

38/96 DS9178 Rev 4

Table 8. CPU/SWIM/debug module/interrupt controller registers

Address Block Register label Register name Reset

status

0x00 7F00

CPU(1)

A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x00

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

0x00 7F05 XL X index register low 0x00

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x03

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

0x00 7F0B to

0x00 7F5F CPU

Reserved area (85 bytes)

0x00 7F60 CFG_GCR Global configuration register 0x00

0x00 7F70

ITC-SPR

ITC_SPR1 Interrupt Software priority register 1 0xFF

0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF

0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF

0x00 7F78

0x00 7F79

Reserved area (2 bytes)

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81

0x00 7F8F

Reserved area (15 bytes)

0x00 7F90

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF

0x00 7F96 DM_CR1 DM Debug module control register 1 0x00

DS9178 Rev 4 39/96

STM8L051F3 Memory and register map

0x00 7F97

DM_CR2 DM Debug module control register 2 0x00

0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B

0x00 7F9F

Reserved area (5 bytes)

1. Accessible by debug module only

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register label Register name Reset

status

Interrupt vector mapping STM8L051F3

40/96 DS9178 Rev 4

6 Interrupt vector mapping

The interrupt vector mapping is described in Table 9.

I Table 9. Interrupt mapping

IRQ

No.

Source

block Description

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)(1)

Vector

address

RESET Reset Yes Yes Yes Yes 0x00 8000

TRAP Software interrupt - - - - 0x00 8004

0TLI

(2) External Top level Interrupt - - - - 0x00 8008

1 FLASH

FLASH end of programing/

write attempted to

protected page interrupt

- - Yes Yes 0x00 800C

2 DMA1 0/1

DMA1 channels 0/1 half

transaction/transaction

complete interrupt

- - Yes Yes 0x00 8010

3 DMA1 2/3

DMA1 channels 2/3 half

transaction/transaction

complete interrupt

- - Yes Yes 0x00 8014

4RTC

RTC alarm A/wakeup/

tamper 1/tamper 2/tamper 3 Yes Yes Yes Yes 0x00 8018

5 PVD PVD interrupt Yes Yes Yes Yes 0x00 801C

6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020

7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024

8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028

9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C

10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030

11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034

12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038

13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C

14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040

15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044

16 Reserved 0x00 8048

17 CLK CLK system clock

switch/CSS interrupt - - Yes Yes 0x00 804C

18 ADC1

ACD1 end of conversion/

analog watchdog/

overrun interrupt

Yes Yes Yes Yes 0x00 8050

DS9178 Rev 4 41/96

STM8L051F3 Interrupt vector mapping

19 TIM2

TIM2 update

/overflow/trigger/break

interrupt

- - Yes Yes 0x00 8054

20 TIM2 TIM2 Capture/Compare

interrupt - - Yes Yes 0x00 8058

21 TIM3

TIM3 Update

/Overflow/Trigger/Break

interrupt

- - Yes Yes 0x00 805C

22 TIM3 TIM3 Capture/Compare

interrupt - - Yes Yes 0x00 8060

23 RI RI trigger interrupt - - Yes - 0x00 8064

24 Reserved 0x00 8068

25 TIM4 TIM4 update/overflow/

trigger interrupt - - Yes Yes 0x00 806C

26 SPI1

SPI1 TX buffer empty/

RX buffer not empty/

error/wakeup interrupt

Yes Yes Yes Yes 0x00 8070

27 USART 1

USART1 transmit data

transmission complete

interrupt

- - Yes Yes 0x00 8074

28 USART 1

USART1 received data

ready/overrun error/

idle line detected/parity

error/global error interrupt

- - Yes Yes 0x00 8078

29 I2C1 I2C1 interrupt(3) Yes Yes Yes Yes 0x00 807C

1. The Low-power wait mode is entered when executing a WFE instruction in Low-power run mode. In WFE mode, the

interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.

When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

Table 9. Interrupt mapping (continued)

IRQ

No.

Source

block Description

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)(1)

Vector

address

Option bytes STM8L051F3

42/96 DS9178 Rev 4

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated memory block.

All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM

address. See Table 10 for details on option byte addresses.

The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for

the ROP and UBCvalues which can only be taken into account when they are modified in

ICP mode (with the SWIM).

Refer to the How to program STM8L and STM8AL Flash program memory and data

EEPROM programming manual (PM0054) and the STM8 SWIM communication protocol

and debug module user manual (UM0470) for information on SWIM programming

procedures.

Table 10. Option byte addresses

Addr. Option name

Option

byte

No.

Option bits Factory

default

setting

76543210

0x00 4800

Read-out

protection

(ROP)

OPT0 ROP[7:0] 0xAA

0x00 4802 UBC (User

Boot code size) OPT1 UBC[7:0] 0x00

0x00 4807 Reserved 0x00

0x00 4808

Independent

watchdog

option

OPT3

[3:0] Reserved WWDG

_HALT

WWDG

_HW

IWDG

_HALT

IWDG

_HW 0x00

0x00 4809

Number of

stabilization

clock cycles for

HSE and LSE

oscillators

OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00

0x00 480A Brownout reset

(BOR)

OPT5

[3:0] Reserved BOR_TH BOR_

ON 0x00

0x00 480B Bootloader

option bytes

(OPTBL)

OPTBL

[15:0] OPTBL[15:0]

0x00

0x00 480C 0x00

DS9178 Rev 4 43/96

STM8L051F3 Option bytes

Table 11. Option byte description

Option

byte

No.

Option description

OPT0

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)

Refer to the “Readout protection” section in the STM8L050J3, STM8L051F3, STM8L052C6,

STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference

manual (RM0031).

OPT1

UBC[7:0] Size of the user boot code area

0x00: UBC is not protected.

0x01: Page 0 is write protected.

0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors.

0x03: Page 0 to 2 reserved for UBC and write protected.

0x7F to 0xFF - All 128 pages reserved for UBC and write protected.

The protection of the memory area not protected by the UBC is enabled through the MASS keys.

Refer to the “User boot code” section in the STM8L050J3, STM8L051F3, STM8L052C6,

STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference

manual (RM0031).

OPT2 Reserved

OPT3

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog off on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

WWDG_HW: Window watchdog

0: Window watchdog activated by software

1: Window watchdog activated by hardware

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode

1: Window watchdog generates a reset when MCU enters Halt mode

OPT4

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

Refer to Table 29: LSE oscillator characteristics on page 62.

Option bytes STM8L051F3

44/96 DS9178 Rev 4

OPT5

BOR_ON:

0: Brownout reset off

1: Brownout reset on

BOR_TH[3:1]: Brownout reset thresholds. Refer to for details on the thresholds according to the value

of BOR_TH bits.

OPTBL

OPTBL[15:0]:

This option is checked by the boot ROM code after reset. Depending on

content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the

CPU jumps to the bootloader or to the reset vector.

Refer to the UM0560 STM8 bootloader user manual for more details.

Table 11. Option byte description (continued)

Option

byte

No.

Option description

DS9178 Rev 4 45/96

STM8L051F3 Electrical parameters

8 Electrical parameters

This section describes the quantification of the given device’s parameters.

8.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

8.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

is indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean±3Σ).

8.1.2 Typical values

Unless otherwise specified, typical data is based on TA = 25 °C, VDD = 3 V. It is given only as

design guidelines and is not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean±2Σ).

8.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

8.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

Figure 5. Pin loading conditions

STM8 PIN

50 pF

MSv37774V1

Electrical parameters STM8L051F3

46/96 DS9178 Rev 4

8.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 6. Pin input voltage

8.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,

Table 13: Current characteristics, and Table 14: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect the device's reliability.

The device's mission profile (application conditions) is compliant with the JEDEC JESD47

Qualification Standard, extended mission profiles are available on demand.

STM8 PIN

MSv37775V1

VIN

Table 12. Voltage characteristics

Symbol Ratings Min Max Unit

VDD- VSS

External supply voltage (including VDDA

and VDD2)(1)

1. All power (VDD1, VDD2, VDDA) and ground (VSS1, VSS2, VSSA) pins must always be connected to the

external power supply.

- 0.3 4.0 V

VIN(2)

2. VIN maximum must always be respected. Refer to Table 13: Current characteristics for maximum allowed

injected current values.

Input voltage on true open-drain pins

(PC0 and PC1) VSS - 0.3 VDD + 4.0

Input voltage on five-volt tolerant (FT)

pins (PA7 and PE0) VSS - 0.3 VDD + 4.0

Input voltage on 3.6 V tolerant (TT) pins VSS - 0.3 4.0

Input voltage on any other pin VSS - 0.3 4.0

VESD Electrostatic discharge voltage

see Absolute maximum

ratings (electrical sensitivity)

on page 86

Table 13. Current characteristics

Symbol Ratings Max. Unit

IVDD Total current into VDD power line (source) 80 mA

IVSS Total current out of VSS ground line (sink) 80

DS9178 Rev 4 47/96

STM8L051F3 Electrical parameters

IIO

Output current sunk by IR_TIM pin (with high sink LED driver

capability) 80

Output current sunk by any other I/O and control pin 25

Output current sourced by any I/Os and control pin - 25

IINJ(PIN)

Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0

Injected current on five-volt tolerant (FT) pins (PA7 and PE0) (1) - 5 / +0

Injected current on 3.6 V tolerant (TT) pins (1) - 5 / +0

Injected current on any other pin (2) - 5 / +5

ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) (3) ± 25

1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must

never be exceeded. Refer to Table 13: Current characteristics for maximum allowed input voltage values.

2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must

never be exceeded. Refer to Table 13: Current characteristics for maximum allowed input voltage values.

3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the

positive and negative injected currents (instantaneous values).

Table 14. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150

° C

TJMaximum junction temperature 150

Table 13. Current characteristics (continued)

Symbol Ratings Max. Unit

Electrical parameters STM8L051F3

48/96 DS9178 Rev 4

8.3 Operating conditions

Subject to general operating conditions for VDD and TA.

8.3.1 General operating conditions

The operating conditions define the conditions under which the device operates correctly

according to its specification (see Table 15).

Table 15. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

fSYSCLK(1) System clock

frequency 1.8 V ≤ VDD < 3.6 V 0 16 MHz

VDD

Standard operating

voltage -1.83.6V

VDDA Analog operating

voltage

Must be at the same

potential as VDD

1.8 3.6 V

PD(2) Power dissipation at

TA= 85 °C TSSOP20 - 181 mW

TATemperature range 1.8 V ≤ VDD < 3.6 V -40 85 °C

Junction temperature

range -40 °C ≤ TA < 85 °C -40 105(3) °C

1. fSYSCLK = fCPU

2. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/Θ

JA with TJmax in this table and Θ

JA in “Thermal characteristics”

table.

3. TJmax is given by the test limit. Above this value, the product behavior is not guaranteed.

DS9178 Rev 4 49/96

STM8L051F3 Electrical parameters

8.3.2 Embedded reset and power control block characteristics

The reset and power block parameters are described in Table 16 and are derived from tests

performed under the ambient temperature conditions summarized in Table 15: General

operating conditions.

Table 16. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tVDD

VDD rise time rate BOR detector

enabled 0(1) -∞ (1)

µs/V

VDD fall time rate BOR detector

enabled 20(1) -∞ (1)

tTEMP Reset release delay VDD rising -3- ms

VPDR Power-down reset threshold Falling edge 1.30(2) 1.50 1.65 V

VBOR0

Brown-out reset threshold 0

(BOR_TH[2:0]=000)

Falling edge 1.67 1.70 1.74

Rising edge 1.69 1.75 1.80

VBOR1

Brown-out reset threshold 1

(BOR_TH[2:0]=001)

Falling edge 1.87 1.93 1.97

Rising edge 1.96 2.04 2.07

VBOR2

Brown-out reset threshold 2

(BOR_TH[2:0]=010)

Falling edge 2.22 2.3 2.35

Rising edge 2.31 2.41 2.44

VBOR3

Brown-out reset threshold 3

(BOR_TH[2:0]=011)

Falling edge 2.45 2.55 2.60

Rising edge 2.54 2.66 2.7

VBOR4

Brown-out reset threshold 4

(BOR_TH[2:0]=100)

Falling edge 2.68 2.80 2.85

Rising edge 2.78 2.90 2.95

VPVD0 PVD threshold 0

Falling edge 1.80 1.84 1.88

Rising edge 1.88 1.94 1.99

VPVD1 PVD threshold 1

Falling edge 1.98 2.04 2.09

Rising edge 2.08 2.14 2.18

VPVD2 PVD threshold 2

Falling edge 2.2 2.24 2.28

Rising edge 2.28 2.34 2.38

VPVD3 PVD threshold 3

Falling edge 2.39 2.44 2.48

Rising edge 2.47 2.54 2.58

VPVD4 PVD threshold 4

Falling edge 2.57 2.64 2.69

Rising edge 2.68 2.74 2.79

VPVD5 PVD threshold 5

Falling edge 2.77 2.83 2.88

Rising edge 2.87 2.94 2.99

VPVD6 PVD threshold 6

Falling edge 2.97 3.05 3.09

Rising edge 3.08 3.15 3.20

1. Guaranteed by design.

2. Guaranteed by characterization results.

Electrical parameters STM8L051F3

50/96 DS9178 Rev 4

Figure 7. POR/BOR thresholds

8.3.3 Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

•All I/O pins in input mode with a static value at VDD or VSS (no load)

•All peripherals are disabled except if explicitly mentioned.

In the following table, data is based on characterization results, unless otherwise specified.

Subject to general operating conditions for VDD and TA.

1.8 V

VDD

Internal NRST

VBOR0

BOR threshold

BOR threshold_0

PDR threshold

with

BOR

without

BOR

Time

with

BOR

Safe reset

Reset

BOR activated by user

for power-down detection

Operatin g power supply

3.6 V

without BOR = battery life extension

VPDR

BOR always active

at power up

Safe reset release

ai17033b

VDD VDD

DS9178 Rev 4 51/96

STM8L051F3 Electrical parameters

Table 17. Total current consumption in Run mode

Symbol Para

meter Conditions(1)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , fCPU=fSYSCLK

Typ

Max

Unit

55 °C 85 °C

IDD(RUN)

Supply

current

in run

mode(2)

2. CPU executing typical data processing

All

peripherals

OFF,

code

executed

from RAM,

VDD from

1.8 V to 3.6 V

HSI RC osc.

(16 MHz)(3)

3. The run from RAM consumption can be approximated with the linear formula:

IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA

fCPU = 125 kHz 0.39 0.47 0.49

fCPU = 1 MHz 0.48 0.56 0.58

fCPU = 4 MHz 0.75 0.84 0.86

fCPU = 8 MHz 1.10 1.20 1.25

fCPU = 16 MHz 1.85 1.93 2.12(5)

HSE external

clock

(fCPU=fHSE)(4)

fCPU = 125 kHz 0.05 0.06 0.09

fCPU = 1 MHz 0.18 0.19 0.20

fCPU = 4 MHz 0.55 0.62 0.64

fCPU = 8 MHz 0.99 1.20 1.21

fCPU = 16 MHz 1.90 2.22 2.23(5)

LSI RC osc.

(typ. 38 kHz) fCPU = fLSI 0.040 0.045 0.046

LSE external

clock

(32.768 kHz)

fCPU = fLSE 0.035 0.040 0.048(5)

IDD(RUN)

Supply

current

in Run

mode

All

peripherals

OFF, code

executed

from Flash,

VDD from

1.8 V to 3.6 V

HSI RC

osc.(6)

fCPU = 125 kHz 0.43 0.55 0.56

fCPU = 1 MHz 0.60 0.77 0.80

fCPU = 4 MHz 1.11 1.34 1.37

fCPU = 8 MHz 1.90 2.20 2.23

fCPU = 16 MHz 3.8 4.60 4.75

HSE external

clock

(fCPU=fHSE) (4)

fCPU = 125 kHz 0.30 0.36 0.39

fCPU = 1 MHz 0.40 0.50 0.52

fCPU = 4 MHz 1.15 1.31 1.40

fCPU = 8 MHz 2.17 2.33 2.44

fCPU = 16 MHz 4.0 4.46 4.52

LSI RC osc. fCPU = fLSI 0.110 0.123 0.130

LSE ext. clock

(32.768

kHz)(7)

fCPU = fLSE 0.100 0.101 0.104

IDD(RUN) DD f(:Pu

Electrical parameters STM8L051F3

52/96 DS9178 Rev 4

Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz

1. Typical current consumption measured with code executed from RAM

4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE

consumption

(IDD HSE) must be added. Refer to Table 28.

5. Tested in production.

6. The run from Flash consumption can be approximated with the linear formula:

IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA

7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE

consumption

(IDD LSE) must be added. Refer to Table 29.

1.50

1.75

2.00

2.25

2.50

2.75

3.00

1.8 2.1 2.6 3.1 3.6

VDD [V]

-40°C

25°C

85°C

ai18213b

IDD(RUN)HSI [mA]

DS9178 Rev 4 53/96

STM8L051F3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Table 18. Total current consumption in Wait mode

Symbol Parameter Conditions(1)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , fCPU = fSYSCLK

Typ

Max

Unit

55°C 85°C

IDD(Wait)

Supply

current in

Wait mode

CPU not

clocked,

all peripherals

OFF,

code executed

from RAM

with Flash in

IDDQ mode(2),

VDD from

1.8 V to 3.6 V

2. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

HSI

fCPU = 125 kHz 0.33 0.39 0.41

fCPU = 1 MHz 0.35 0.41 0.44

fCPU = 4 MHz 0.42 0.51 0.52

fCPU = 8 MHz 0.52 0.57 0.58

fCPU = 16 MHz 0.68 0.76 0.79

HSE external

clock

(fCPU=fHSE)(3)

3. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE

consumption

(IDD HSE) must be added. Refer to Table 28.

fCPU = 125 kHz 0.032 0.056 0.068

fCPU = 1 MHz 0.078 0.121 0.144

fCPU = 4 MHz 0.218 0.26 0.30

fCPU = 8 MHz 0.40 0.52 0.57

fCPU = 16 MHz 0.760 1.01 1.05

LSI fCPU = fLSI 0.035 0.044 0.046

LSE(4)

external clock

(32.768 kHz)

fCPU = fLSE 0.032 0.036 0.038

IDD(Wait)

Supply

current in

Wait

mode

CPU not

clocked,

all peripherals

OFF,

code executed

from Flash,

VDD from

1.8 V to 3.6 V

HSI

fCPU = 125 kHz 0.38 0.48 0.49

fCPU = 1 MHz 0.41 0.49 0.51

fCPU = 4 MHz 0.50 0.57 0.58

fCPU = 8 MHz 0.60 0.66 0.68

fCPU = 16 MHz 0.79 0.84 0.86

HSE(3)

external clock

(fCPU=HSE)

fCPU = 125 kHz 0.06 0.08 0.09

fCPU = 1 MHz 0.10 0.17 0.18

fCPU = 4 MHz 0.24 0.36 0.39

fCPU = 8 MHz 0.50 0.58 0.61

fCPU = 16 MHz 1.00 1.08 1.14

LSI fCPU = fLSI 0.055 0.058 0.065

LSE(4)

external clock

(32.768 kHz)

fCPU = fLSE 0.051 0.056 0.060

'DDMait) DD CPU z "*7“

Electrical parameters STM8L051F3

54/96 DS9178 Rev 4

Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1)

1. Typical current consumption measured with code executed from Flash memory.

4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE

consumption

(IDD HSE) must be added. Refer to Table 29.

500

550

600

650

700

750

800

850

900

950

1000

1.8 2.1 2.6 3.1 3.6

VDD [V]

IDD(WAIT)HSI

[μA]

-40°C

25°C

85°C

ai18214b

IDDILPR) DD

DS9178 Rev 4 55/96

STM8L051F3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source)

Table 19. Total current consumption and timing in Low power run mode

at VDD = 1.8 V to 3.6 V

Symbol Parameter Conditions(1) Typ Max Unit

IDD(LPR) Supply current in

Low power run mode

LSI RC osc.

(at 38 kHz)

all peripherals OFF

TA = -40 °C to 25 °C 5.1 5.4

μA

TA = 55 °C 5.7 6

TA = 85 °C 6.8 7.5

with TIM2 active(2)

TA = -40 °C to 25 °C 5.4 5.7

TA = 55 °C 6.0 6.3

TA = 85 °C 7.2 7.8

LSE (3) external

clock

(32.768 kHz)

all peripherals OFF

TA = -40 °C to 25 °C 5.25 5.6

TA = 55 °C 5.67 6.1

TA = 85 °C 5.85 6.3

with TIM2 active (2)

TA = -40 °C to 25 °C 5.59 6

TA = 55 °C 6.10 6.4

TA = 85 °C 6.30 7

1. No floating I/Os

2. Timer 2 clock enabled and counter running

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(IDD LSE) must be added. Refer to Table 29

ai18216b

IDD(LPR)LSI

[μA]

-40° C

25° C

85° C

VDD [V]

1.8 2.1 2.6 3.1 3.6

DD(LPW) DD

Electrical parameters STM8L051F3

56/96 DS9178 Rev 4

In the following table, data is based on characterization results, unless otherwise specified.

Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source)

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V

Symbol Parameter Conditions(1) Typ Max Unit

IDD(LPW)

Supply current in

Low power wait

mode

LSI RC osc.

(at 38 kHz)

all peripherals OFF

TA = -40 °C to 25 °C 33.3

μA

TA = 55 °C 3.3 3.6

TA = 85 °C 4.4 5

with TIM2 active(2)

TA = -40 °C to 25 °C 3.4 3.7

TA = 55 °C 3.7 4

TA = 85 °C 4.8 5.4

LSE external

clock(3)

(32.768 kHz)

all peripherals OFF

TA = -40 °C to 25 °C 2.35 2.7

TA = 55 °C 2.42 2.82

TA = 85 °C 3.10 3.71

with TIM2 active (2)

TA = -40 °C to 25 °C 2.46 2.75

TA = 55 °C 2.50 2.81

TA = 85 °C 3.16 3.82

1. No floating I/Os.

2. Timer 2 clock enabled and counter is running.

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(IDD LSE) must be added. Refer to Table 29.

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

IDD(LPW )L SI

[μA]

-40°C

25°C

85°C

2.11.8 2.6 3.1 3.6

VDD [V]

ai18217b

DS9178 Rev 4 57/96

STM8L051F3 Electrical parameters

In the following table, data is based on characterization results, unless otherwise specified.

Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V

Symbol Parameter Conditions (1) Typ Max Unit

IDD(AH) Supply current in

Active-halt mode

LSI RC (at 38 kHz)

TA = -40 °C to 25 °C 0.9 2.1

μA

TA = 55 °C 1.2 3

TA = 85 °C 1.5 3.4

LSE external clock (32.768

kHz)(2)

TA = -40 °C to 25 °C 0.5 1.2

TA = 55 °C 0.62 1.4

TA = 85 °C 0.88 2.1

IDD(WUFAH)

Supply current during

wakeup time from

Active-halt mode

(using HSI)

--2.4-mA

tWU_HSI(AH)(3)(4)

Wakeup time from

Active-halt mode to

Run mode (using HSI)

--4.77μs

tWU_LSI(AH)(3)

(4)

Wakeup time from

Active-halt mode to

Run mode (using LSI)

- - 150 - μs

1. No floating I/O, unless otherwise specified.

2. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(IDD LSE) must be added. Refer to Table 29.

3. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after tWU.

4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE

external crystal

Symbol Parameter Condition(1) Typ Unit

IDD(AH) (2) Supply current in Active-halt

mode

VDD = 1.8 V

LSE 1.15

µA

LSE/32(3) 1.05

VDD = 3 V

LSE 1.30

LSE/32(3) 1.20

VDD = 3.6 V

LSE 1.45

LSE/32(3) 1.35

1. No floating I/O, unless otherwise specified.

2. Based on measurements on bench with 32.768 kHz external crystal oscillator.

3. RTC clock is LSE divided by 32.

Electrical parameters STM8L051F3

58/96 DS9178 Rev 4

In the following table, data is based on characterization results, unless otherwise specified.

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V

Symbol Parameter Condition(1) Typ Max Unit

IDD(Halt)

Supply current in Halt mode

(Ultra-low-power ULP bit =1 in

the PWR_CSR2 register)

TA = -40 °C to 25 °C 350 1400(2)

nATA = 55 °C 580 2000

TA = 85 °C 1160 2800(2)

IDD(WUHalt)

Supply current during wakeup

time from Halt mode (using

HSI)

-2.4-mA

tWU_HSI(Halt)(3)(4) Wakeup time from Halt to Run

mode (using HSI) -4.77µs

tWU_LSI(Halt) (3)(4) Wakeup time from Halt mode

to Run mode (using LSI) -150-µs

1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified.

2. Tested in production.

3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

4. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after tWU.

DS9178 Rev 4 59/96

STM8L051F3 Electrical parameters

Current consumption of on-chip peripherals

Table 24. Peripheral current consumption

Symbol Parameter Typ.

VDD = 3.0 V Unit

IDD(TIM2) TIM2 supply current (1) 8

µA/MHz

IDD(TIM3) TIM3 supply current (1) 8

IDD(TIM4) TIM4 timer supply current (1) 3

IDD(USART1) USART1 supply current (2) 6

IDD(SPI1) SPI1 supply current (2) 3

IDD(I2C1) I2C1 supply current (2) 5

IDD(DMA1) DMA1 supply current(2) 3

IDD(WWDG) WWDG supply current(2) 2

IDD(ALL) Peripherals ON(3) 44 µA/MHz

IDD(ADC1) ADC1 supply current(4) 1500

µA

IDD(COMP1) Comparator 1 supply current(5) 0.160

IDD(COMP2) Comparator 2 supply current(5) Slow mode 2

Fast mode 5

IDD(PVD/BOR)

Power voltage detector and brownout Reset unit supply

current (6) 2.6

IDD(BOR) Brownout Reset unit supply current (6) 2.4

IDD(IDWDG) Independent watchdog supply current

including LSI supply

current 0.45

excluding LSI

supply current 0.05

1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The

CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.

2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.

Not tested in production.

3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.

4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.

5. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2

enabled with static inputs. Supply current of internal reference voltage excluded.

6. Including supply current of internal reference voltage.

Electrical parameters STM8L051F3

60/96 DS9178 Rev 4

8.3.4 Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

Table 25. Current consumption under external reset

Symbol Parameter Conditions Typ Unit

IDD(RST)

Supply current under

external reset (1)

All pins are externally

tied to VDD

VDD = 1.8 V 48

µAVDD = 3 V 76

VDD = 3.6 V 91

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

Table 26. HSE external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext

External clock source

frequency(1) -1-16MHz

VHSEH OSC_IN input pin high level

voltage - 0.7 x VDD -V

VHSEL OSC_IN input pin low level

voltage -V

SS - 0.3 x VDD

Cin(HSE) OSC_IN input capacitance(1) --2.6-pF

ILEAK_HSE OSC_IN input leakage current VSS < VIN < VDD --±1µA

1. Guaranteed by design.

Table 27. LSE external clock characteristics

Symbol Parameter Min Typ Max Unit

fLSE_ext External clock source frequency(1) - 32.768 - kHz

VLSEH(2) OSC32_IN input pin high level voltage 0.7 x VDD -V

VLSEL(2) OSC32_IN input pin low level voltage VSS - 0.3 x VDD

Cin(LSE) OSC32_IN input capacitance(1) -0.6-pF

ILEAK_LSE OSC32_IN input leakage current - - ±1 µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

Lego m RF osc,‘ N CI Ftsscnawr a eonsmwon comm +88%? g“: 05.ch sTMa

DS9178 Rev 4 61/96

STM8L051F3 Electrical parameters

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All

the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Figure 12. HSE oscillator circuit diagram

HSE oscillator critical gm formula

Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),

Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),

CL1=CL2=C: Grounded external capacitance

gm >> gmcrit

Table 28. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSE

High speed external oscillator

frequency -1-16MHz

RFFeedback resistor - - 200 - kΩ

C(1) Recommended load capacitance (2) --20-pF

IDD(HSE) HSE oscillator power consumption

C = 20 pF,

fOSC = 16 MHz --

2.5 (startup)

0.7 (stabilized)(3)

C = 10 pF,

fOSC =16 MHz --

2.5 (startup)

0.46 (stabilized)(3)

gmOscillator transconductance - 3.5(3) --mA/V

tSU(HSE)(4) Startup time VDD is stabilized - 1 - ms

1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.

Refer to crystal manufacturer for more details

3. Guaranteed by design.

4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This

value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

gmcrit 2Π× fHSE

×()

2Rm

×2Co C+()

\ \ STME \ \ oscpu'r

Electrical parameters STM8L051F3

62/96 DS9178 Rev 4

LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All

the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Figure 13. LSE oscillator circuit diagram

Table 29. LSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fLSE

Low speed external oscillator

frequency - - 32.768 - kHz

RFFeedback resistor ΔV = 200 mV - 1.2 - MΩ

C(1) Recommended load capacitance (2) --8-pF

IDD(LSE) LSE oscillator power consumption

---1.4

(3) µA

VDD = 1.8 V - 450 -

nAVDD = 3 V - 600 -

VDD = 3.6 V - 750 -

gmOscillator transconductance - 3(3) --µA/V

tSU(LSE)(4) Startup time VDD is stabilized - 1 - s

1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.

Refer to crystal manufacturer for more details.

3. Guaranteed by design.

4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.

This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

DS9178 Rev 4 63/96

STM8L051F3 Electrical parameters

Internal clock sources

Subject to general operating conditions for VDD, and TA.

High speed internal RC oscillator (HSI)

In the following table, data is based on characterization results, not tested in production,

unless otherwise specified.

Figure 14. Typical HSI frequency vs VDD

Table 30. HSI oscillator characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

fHSI Frequency VDD = 3.0 V - 16 - MHz

ACCHSI

Accuracy of HSI

oscillator (factory

calibrated)

VDD = 3.0 V, TA = 25 °C -1 (2)

-2.5 -1(2)

1.8 V ≤ VDD ≤ 3.6 V,

-40 °C ≤ TA ≤ 85 °C -5 - 5 %

TRIM HSI user trimming

step(3)

Trimming code ≠ multiple of 16 - 0.4 0.7 %

Trimming code = multiple of 16 - - ± 1.5 %

tsu(HSI)

HSI oscillator setup

time (wakeup time) --3.76

(4) µs

IDD(HSI)

HSI oscillator power

consumption - - 100 140(4) µA

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Tested in production.

3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16

(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for

more details.

4. Guaranteed by design.

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

-40°C

25°C

85°C

VDD [V]

HSI frequency [MHz]

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

ai18218c

Electrical parameters STM8L051F3

64/96 DS9178 Rev 4

Low speed internal RC oscillator (LSI)

In the following table, data is based on characterization results, not tested in production.

Figure 15. Typical LSI frequency vs. VDD

Table 31. LSI oscillator characteristics

Symbol Parameter (1)

1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.

Conditions(1) Min Typ Max Unit

fLSI Frequency - 26 38 56 kHz

tsu(LSI) LSI oscillator wakeup time - - - 200(2)

2. Guaranteed by design.

µs

IDD(LSI)

LSI oscillator frequency

drift(3)

3. This is a deviation for an individual part, once the initial frequency has been measured.

0 °C ≤ TA ≤ 85 °C -12 - 11 %

1.8 2.1 2.6 3.1 3.6

-40°C

25°C

85°C

ai18219b

VDD [V]

LSI frequency [kHz]

DS9178 Rev 4 65/96

STM8L051F3 Electrical parameters

8.3.5 Memory characteristics

TA = -40 to 85 °C unless otherwise specified.

Flash memory

Table 32. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode (1)

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware

registers (only in Halt mode). Guaranteed by characterization.

Halt mode (or Reset) 1.8 - - V

Table 33. Flash program and data EEPROM memory

Symbol Parameter Conditions Min Typ Max

(1) Unit

VDD

Operating voltage

(all modes, read/write/erase) fSYSCLK = 16 MHz 1.8 3.6 V

tprog

Programming time for 1 or 64 bytes (block)

erase/write cycles (on programmed byte) 6ms

Programming time for 1 to 64 bytes (block)

write cycles (on erased byte) 3ms

Iprog Programming/ erasing consumption

TA=+25 °C, VDD = 3.0 V

0.7 mA

TA=+25 °C, VDD = 1.8 V

tRET(2)

Data retention (program memory) after 100

erase/write cycles at TA= –40 to +85 °C TRET = +85 °C 30(1)

years

Data retention (data memory) after 100000

erase/write cycles at TA= –40 to +85 °C TRET = +85 °C 30(1)

NRW (3)

Erase/write cycles (program memory)

TA = –40 to +85 °C

100(1) cycles

Erase/write cycles (data memory) 100(1)

(4) kcycles

1. Guaranteed by characterization results.

2. Conforming to JEDEC JESD22a117

3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation

addresses a single byte.

4. Data based on characterization performed on the whole data memory.

Electrical parameters STM8L051F3

66/96 DS9178 Rev 4

8.3.6 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard pins) should be avoided during normal product operation.

However, in order to give an indication of the robustness of the microcontroller in cases

when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current

injection on adjacent pins or other functional failure (for example reset, oscillator frequency

deviation, LCD levels, etc.).

The test results are given in the following table.

8.3.7 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 34. I/O current injection susceptibility

Symbol Description

Functional susceptibility

Unit

Negative

injection

Positive

injection

IINJ

Injected current on true open-drain pins (PC0 and

PC1) -5 +0

Injected current on all five-volt tolerant (FT) pins -5 +0

Injected current on all 3.6 V tolerant (TT) pins -5 +0

Injected current on any other pin -5 +5

DS9178 Rev 4 67/96

STM8L051F3 Electrical parameters

Table 35. I/O static characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

VIL Input low level voltage(2)

Input voltage on true open-drain

pins (PC0 and PC1) VSS-0.3 0.3 x VDD

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0)

VSS-0.3 0.3 x VDD

Input voltage on 3.6 V tolerant

(TT) pins VSS-0.3 0.3 x VDD

Input voltage on any other pin VSS-0.3 0.3 x VDD

VIH Input high level voltage (2)

Input voltage on true open-drain

pins (PC0 and PC1)

with VDD < 2 V

0.70 x VDD

5.2

Input voltage on true open-drain

pins (PC0 and PC1)

with VDD ≥ 2 V

5.5

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0) with VDD < 2 V

0.70 x VDD

5.2

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0) with VDD ≥ 2 V

5.5

Input voltage on 3.6 V tolerant

(TT) pins 3.6

Input voltage on any other pin 0.70 x VDD VDD+0.3

Vhys

Schmitt trigger voltage

hysteresis (3)

I/Os 200

True open drain I/Os 200

Ilkg Input leakage current (4)

VSS≤ VIN≤ VDD

High sink I/Os --50

(5)

VSS≤ VIN≤ VDD

True open drain I/Os - - 200(5)

VSS≤ VIN≤ VDD

PA0 with high sink LED driver

capability

- - 200(5)

RPU

Weak pull-up equivalent

resistor(2)(6) VIN=VSS 30 45 60 kΩ

CIO I/O pin capacitance 5 pF

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in

Figure 19).

74,:ng

Electrical parameters STM8L051F3

68/96 DS9178 Rev 4

Figure 16. Typical VIL and VIH vs VDD (high sink I/Os)

Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os)

0.5

1.5

2.5

1.8 2.1 2.6 3.1 3.6

-40°C

25°C

85°C

ai18220c

VIL and VIH [V]

VDD [V]

0.5

1.5

2.5

1.8 2.1 2.6 3.1 3.6

-40°C

25°C

85°C

ai18221b

VIL and VIH [V]

VDD [V]

DD IN SS nu DD VIN Vss

DS9178 Rev 4 69/96

STM8L051F3 Electrical parameters

Figure 18. Typical pull-up resistance RPU vs VDD with VIN=VSS

Figure 19. Typical pull-up current Ipu vs VDD with VIN=VSS

-40°C

25°C

85°C

ai18222b

Pull-up resistance [kΩ]

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

VDD [V]

100

120

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

-40°C

25°C

85°C

ai18223b

Pull-up current [μA]

VDD [V]

Electrical parameters STM8L051F3

70/96 DS9178 Rev 4

Output driving current

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 36. Output driving current (high sink ports)

I/O

Type Symbol Parameter Conditions Min Max Unit

High sink

VOL (1)

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current

characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output low level voltage for an I/O pin

IIO = +2 mA,

VDD = 3.0 V -0.45V

IIO = +2 mA,

VDD = 1.8 V -0.45V

IIO = +10 mA,

VDD = 3.0 V -0.7V

VOH (2)

2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13: Current

characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

Output high level voltage for an I/O pin

IIO = -2 mA,

VDD = 3.0 V VDD-0.45 -V

IIO = -1 mA,

VDD = 1.8 V VDD-0.45 -V

IIO = -10 mA,

VDD = 3.0 V VDD-0.7 - V

Table 37. Output driving current (true open drain ports)

I/O

Type Symbol Parameter Conditions Min Max Unit

Open drain

VOL (1)

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current

characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output low level voltage for an I/O pin

IIO = +3 mA,

VDD = 3.0 V -0.45

IIO = +1 mA,

VDD = 1.8 V -0.45

Table 38. Output driving current (PA0 with high sink LED driver capability)

I/O

Type Symbol Parameter Conditions Min Max Unit

VOL (1)

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13: Current

characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output low level voltage for an I/O pin IIO = +20 mA,

VDD = 2.0 V -0.45V

Figure 20. Typ. V @ V = 3.0 V (high sink Figure 21. Typ. V @ V =1.a v (high sink Figure 22. Typ. V @ V = 3.0 V (true open Figure 23. Typ. V @ V = 1.8 V (true open Figure 24. Typ. v _v @ v D = 3.0 v (high Figure 25. Typ. V v @v =1.8V[high / .A/4

DS9178 Rev 4 71/96

STM8L051F3 Electrical parameters

Figure 20. Typ. VOL @ VDD = 3.0 V (high sink

ports)

Figure 21. Typ. VOL @ VDD = 1.8 V (high sink

ports)

0.25

0.5

0.75

02468101214161820

IOL [mA]

VOL [V]

-40°C

25°C

85°C

ai18226V2

0.1

0.2

0.3

0.4

0.5

0.6

0.7

012345678

IOL [mA]

VOL [V]

-40°C

25°C

85°C

ai18227V2

Figure 22. Typ. VOL @ VDD = 3.0 V (true open

drain ports)

Figure 23. Typ. VOL @ VDD = 1.8 V (true open

drain ports)

ai18228V2

0.1

0.2

0.3

0.4

0.5

01234567

IOL [mA]

VOL [V]

-40°C

25°C

85°C

0.1

0.2

0.3

0.4

0.5

01234567

IOL [mA]

VOL [V]

-40°C

25°C

85°C

ai18229V2

Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high

sink ports)

Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high

sink ports)

0.25

0.5

0.75

1.25

1.5

1.75

0 2 4 6 8 101214161820

IOH [mA]

VDD - VOH [V]

-40°C

25°C

85°C

ai12830V2

0.1

0.2

0.3

0.4

0.5

01234567

IOH [mA]

VDD - VOH [V]

-40°C

25°C

85°C

ai18231V2

PU DD

Electrical parameters STM8L051F3

72/96 DS9178 Rev 4

NRST pin

Subject to general operating conditions for VDD and TA unless otherwise specified.

Figure 26. Typical NRST pull-up resistance RPU vs VDD

Table 39. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level voltage (1) -VSS -0.8

VIH(NRST) NRST input high level voltage (1) -1.4-

VDD

VOL(NRST) NRST output low level voltage (1)

IOL = 2 mA

for 2.7 V ≤ VDD ≤ 3.6 V --

0.4

IOL = 1.5 mA

for VDD < 2.7 V --

VHYST NRST input hysteresis(3) -10%VDD

(2) --mV

RPU(NRST) NRST pull-up equivalent resistor

(1) -304560kΩ

VF(NRST) NRST input filtered pulse (3) ---50

VNF(NRST) NRST input not filtered pulse (3) - 300 - -

1. Guaranteed by characterization results.

2. 200 mV min.

3. Data guaranteed by design, not tested in production.

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

VDD [V]

-40°C

25°C

85°C

ai18224b

Pull-up resistance [kΩ]

DS9178 Rev 4 73/96

STM8L051F3 Electrical parameters

Figure 27. Typical NRST pull-up current Ipu vs VDD

The reset network shown in Figure 28 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified

in Table 39. Otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be

reduced to limit the charge/discharge current. If the NRST signal is used to reset the

external circuitry, attention must be paid to the charge/discharge time of the external

capacitor to fulfill the external devices reset timing conditions. The minimum recommended

capacity is 10 nF.

Figure 28. Recommended NRST pin configuration

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

Pull-up current [μA]

120

100

VDD [V]

-40°C

25°C

85°C

ai18225b

EXTERNAL

RESET

CIRCUIT

STM8

Filter

RPU

VDD

INTERNAL RESET

NRST

0.1 µF

(Optional)

Electrical parameters STM8L051F3

74/96 DS9178 Rev 4

8.3.8 Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Table 40 are derived from tests

performed under ambient temperature, fSYSCLK frequency and VDD supply voltage

conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on

the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 40. SPI1 characteristics

Symbol Parameter Conditions(1) Min Max Unit

fSCK

1/tc(SCK)

SPI1 clock frequency

Master mode 0 8

MHz

Slave mode 0 8

tr(SCK)

tf(SCK)

SPI1 clock rise and fall

time Capacitive load: C = 30 pF - 30

tsu(NSS)(2) NSS setup time Slave mode 4 x 1/fSYSCLK -

th(NSS)(2) NSS hold time Slave mode 80 -

tw(SCKH)(2)

tw(SCKL)(2) SCK high and low time Master mode,

fMASTER = 8 MHz, fSCK= 4 MHz 105 145

tsu(MI) (2)

tsu(SI)(2) Data input setup time

Master mode 30 -

Slave mode 3 -

th(MI) (2)

th(SI)(2) Data input hold time

Master mode 15 -

Slave mode 0 -

ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK

tdis(SO)(2)(4) Data output disable time Slave mode 30 -

tv(SO) (2) Data output valid time Slave mode (after enable edge) - 60

tv(MO)(2) Data output valid time Master mode (after enable

edge) -20

th(SO)(2)

Data output hold time

Slave mode (after enable edge) 15 -

th(MO)(2) Master mode (after enable

edge) 1-

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

NSS Input \ I ‘sm N55 1 ‘c(5CK7—ﬁ ‘mNssw‘—" 5cm)”. ,1} ‘v1SD)H ‘h(so)«—~ N‘NSCK) ‘ms(50) <—>3 ‘ ‘ «(sen ‘ MSB OUT X 3sz OUT X LSB OUT )- ‘smsnﬁ—Q‘L Mosl ‘ " INPUT X 1 M88 IN x BIT: IN X LSB \N X Elms)!" mm [ —a; ﬂ—m i r= ﬁb— 1——

DS9178 Rev 4 75/96

STM8L051F3 Electrical parameters

Figure 29. SPI1 timing diagram - slave mode and CPHA=0

Figure 30. SPI1 timing diagram - slave mode and CPHA=1(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

ai14135b

NSS input

tSU(NSS) tc(SCK) th(NSS)

SCK input

CPHA=1

CPOL=0

CPHA=1

CPOL=1

tw(SCKH)

tw(SCKL)

ta(SO) tv(SO) th(SO) tr(SCK)

tf(SCK) tdis(SO)

MISO

OUTPUT

MOSI

INPUT

tsu(SI) th(SI)

MSB OUT

MSB IN

BIT6 OUT LSB OUT

LSB IN

BIT 1 IN

SCK mpm SCK mpm ngh NSS mpul W50 ‘SMMIW—HE «$§§§ET)«—> __ 3 ”$223 INPUT X : msaw 3 X swim 1 LSB‘N FWWA‘ chaff); X M55 OUT 1 X B‘TT 0:UT i X LSB OUT X ‘x/(Mth—h1 mm)?»1 Emma

Electrical parameters STM8L051F3

76/96 DS9178 Rev 4

Figure 31. SPI1 timing diagram - master mode(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

DS9178 Rev 4 77/96

STM8L051F3 Electrical parameters

I2C - Inter IC control interface

Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.

The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C

communication protocol described in the following table with the restriction mentioned

below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Note: For speeds around 200 kHz, the achieved speed can have a± 5% tolerance

For other speed ranges, the achieved speed can have a± 2% tolerance

The above variations depend on the accuracy of the external components used.

Table 41. I2C characteristics

Symbol Parameter

Standard mode

I2C Fast mode I2C(1)

Unit

Min(2) Max (2) Min (2) Max (2)

tw(SCLL) SCL clock low time 4.7 - 1.3 -

μs

tw(SCLH) SCL clock high time 4.0 - 0.6 -

tsu(SDA) SDA setup time 250 - 100 -

th(SDA) SDA data hold time 0 - 0 900

tr(SDA)

tr(SCL)

SDA and SCL rise time - 1000 - 300

tf(SDA)

tf(SCL)

SDA and SCL fall time - 300 - 300

th(STA) START condition hold time 4.0 - 0.6 -

μs

tsu(STA) Repeated START condition setup

time 4.7 - 0.6 -

tsu(STO) STOP condition setup time 4.0 - 0.6 - μs

tw(STO:STA) STOP to START condition time (bus

free) 4.7 - 1.3 - μs

CbCapacitive load for each bus line - 400 - 400 pF

1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).

2. Data based on standard I2C protocol requirement, not tested in production.

Fr: BUS l‘ ‘smsm ‘ 'wsmsm SBA . 7“ . ‘ ‘ . H ‘ "5"“ : ‘kuxsm 'nlsml' ’ 1 , m ‘ . ‘ , . h F‘— Imsm mm ‘Mscm Tm; «as'cu Kw

Electrical parameters STM8L051F3

78/96 DS9178 Rev 4

Figure 32. Typical application with I2C bus and timing diagram 1)

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD

DS9178 Rev 4 79/96

STM8L051F3 Electrical parameters

8.3.9 Embedded reference voltage

In the following table, data is based on characterization results, not tested in production,

unless otherwise specified.

8.3.10 12-bit ADC1 characteristics

In the following table, data is guaranteed by design, not tested in production.

Table 42. Reference voltage characteristics

Symbol Parameter Conditions Min Typ Max. Unit

IREFINT

Internal reference voltage

consumption - - 1.4 - µA

TS_VREFINT(1)(2) ADC sampling time when reading

the internal reference voltage --510µs

IBUF(2) Internal reference voltage buffer

consumption (used for ADC) - - 13.5 25 µA

VREFINT out Reference voltage output - 1.202(3) 1.224 1.242(3) V

ILPBUF(2) Internal reference voltage low-

power buffer consumption - - 730 1200 nA

IREFOUT(2) Buffer output current(4) ---1µA

CREFOUT Reference voltage output load - - - 50 pF

tVREFINT

Internal reference voltage startup

time --23ms

tBUFEN(2) Internal reference voltage buffer

startup time once enabled (1) ---10µs

ACCVREFINT

Accuracy of VREFINT stored in the

VREFINT_Factory_CONV byte(5) ---± 5mV

STABVREFINT

Stability of VREFINT over

temperature

-40 °C ≤ TA ≤ 85

°C -2050ppm/°C

Stability of VREFINT over

temperature 0 °C ≤ TA ≤ 50 °C - - 20 ppm/°C

STABVREFINT

Stability of VREFINT after 1000

hours ---TBDppm

1. Defined when ADC output reaches its final value ±1/2LSB

2. Data guaranteed by design.

3. Tested in production at VDD = 3 V ±10 mV.

4. To guaranty less than 1% VREFOUT deviation.

5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.

Electrical parameters STM8L051F3

80/96 DS9178 Rev 4

Table 43. ADC1 characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 - 3.6 V

VREF+ Reference supply

voltage

2.4 V ≤ VDDA≤ 3.6 V 2.4 - VDDA V

1.8 V ≤ VDDA≤ 2.4 V VDDA V

VREF- Lower reference voltage - VSSA V

IVDDA Current on the VDDA

input pin - - 1000 1450 µA

IVREF+ Current on the VREF+

input pin

400

700

(peak)(1) µA

-- 450

(average)(1) µA

VAIN Conversion voltage

range -0(2) -VREF+ -

TATemperature range - -40 - 85 °C

RAIN External resistance on

VAIN

---

50(3) kΩ

---

CADC Internal sample and hold

capacitor

-- -

fADC ADC sampling clock

frequency

2.4 V≤ VDDA≤ 3.6 V

without zooming 0.320 - 16 MHz

1.8 V≤ VDDA≤ 2.4 V

with zooming 0.320 - 8 MHz

fCONV 12-bit conversion rate VAIN on all slow

channels --

760(4) kHz

fTRIG External trigger

frequency ---

tconv 1/fADC

tLAT External trigger latency - - - 3.5 1/fSYSCLK

tSSampling time

VAIN on slow channels

VDDA < 2.4 V 0.86(4) --µs

VAIN on slow channels

2.4 V ≤ VDDA≤ 3.6 V 0.41(4) --µs

tconv 12-bit conversion time

- 12 + tS 1/fADC

16 MHz 1(4) µs

tWKUP Wakeup time from OFF

state ---3µs

tIDLE(5) Time before a new

conversion

TA = +25 °C - - 1(6) s

TA = +70 °C - - 20(6) ms

tVREFINT

Internal reference

voltage startup time ---

refer to

Table 42 ms

DS9178 Rev 4 81/96

STM8L051F3 Electrical parameters

1. The current consumption through VREF is composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at

1Msps

2. VREF- or VDDA must be tied to ground.

3. Guaranteed by design.

4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ.

5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.

6. The tIDLE maximum value is ∞ on the “Z” revision code of the device.

VDDA VDDA DDA VREF+

Electrical parameters STM8L051F3

82/96 DS9178 Rev 4

In the following three tables, data is guaranteed by characterization result, not tested in

production.

Table 44. ADC1 accuracy with VDDA = 3.3 V to 2.5 V

Symbol Parameter Conditions Typ Max Unit

DNL Differential non linearity

fADC = 16 MHz 1 1.6

LSB

fADC = 8 MHz 1 1.6

fADC = 4 MHz 1 1.5

INL Integral non linearity

fADC = 16 MHz 1.2 2

fADC = 8 MHz 1.2 1.8

fADC = 4 MHz 1.2 1.7

TUE Total unadjusted error

fADC = 16 MHz 2.2 3.0

fADC = 8 MHz 1.8 2.5

fADC = 4 MHz 1.8 2.3

Offset Offset error

fADC = 16 MHz 1.5 2

LSB

fADC = 8 MHz 1 1.5

fADC = 4 MHz 0.7 1.2

Gain Gain error

fADC = 16 MHz

11.5fADC = 8 MHz

fADC = 4 MHz

Table 45. ADC1 accuracy with VDDA = 2.4 V to 3.6 V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 1.7 3 LSB

TUE Total unadjusted error 24LSB

Offset Offset error 1 2 LSB

Gain Gain error 1.5 3 LSB

Table 46. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 23LSB

TUE Total unadjusted error 35LSB

Offset Offset error 2 3 LSB

Gain Gain error 2 3 LSB

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DS9178 Rev 4 83/96

STM8L051F3 Electrical parameters

Figure 33. ADC1 accuracy characteristics

Figure 34. Typical connection diagram using the ADC

1. Refer to Table 47 for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

Figure 35. Maximum dynamic current consumption on VREF+ supply pin during ADC

conversion

ai17090f

STM8

IL± 50nA

12-bit

converter

Sample and hold ADC

converter

AIN

(1)

AINx

0.6V

parasitic

(2)

ADC

ADC(1)

MS46324V1

Sampling

(n cycles) Conversion (12 cycles)

ADC clock

ref+

700 μA

300 μA

RAIN ADC VREn DDA

Electrical parameters STM8L051F3

84/96 DS9178 Rev 4

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 36 or Figure 37,

depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF

capacitors should be used. They should be placed as close as possible to the chip.

Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)

Table 47. RAIN max for fADC = 16 MHz(1)

1. Guaranteed by design.

Ts (cycles) Ts

(µs)

RAIN max (kohm)

Slow channels

2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V

4 0.25 Not allowed Not allowed

9 0.5625 0.8 Not allowed

16 1 2.0 0.8

24 1.5 3.0 1.8

48 3 6.8 4.0

96 6 15.0 10.0

192 12 32.0 25.0

384 24 50.0 50.0

Supply

External

reference

STM8L

VREF+

VDDA

VSSA/VREF-

1 μF // 10 nF

ai17031c

VREh DDA

DS9178 Rev 4 85/96

STM8L051F3 Electrical parameters

Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA)

8.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),

the product is stressed by two electromagnetic events until a failure occurs (indicated by the

LEDs).

•ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000 standard.

•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms

with the IEC 61000 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Prequalification trials

STM8L

Supply

ai17032d

1 μF // 10 nF

VREF+/VDDA

VREF-/VSSA

Electrical parameters STM8L051F3

86/96 DS9178 Rev 4

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O

ports), the product is monitored in terms of emission. This emission test is in line with the

norm IEC61967-2 which specifies the board and the loading of each pin.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models

can be simulated: human body model and charge device model. This test conforms to the

JESD22-A114A/A115A standard.

Table 48. EMS data

Symbol Parameter Conditions Level/

Class

VFESD

Voltage limits to be applied on

any I/O pin to induce a functional

disturbance

VDD = 3.3 V, TA = +25 °C,

fCPU= 16 MHz,

conforms to IEC 61000

VEFTB

Fast transient voltage burst limits

to be applied through 100 pF on

VDD and VSS pins to induce a

functional disturbance

VDD = 3.3 V, TA = +25 °C,

fCPU = 16 MHz,

conforms to IEC 61000

Using HSI 4A

Using HSE 2B

Table 49. EMI data (1)

1. Not tested in production.

Symbol Parameter Conditions Monitored

frequency band

Max vs.

Unit

16 MHz

SEMI Peak level

VDD = 3.6 V,

TA = +25 °C,

LQFP32

conforming to

IEC61967-2

0.1 MHz to 30 MHz -3

dBμV30 MHz to 130 MHz 9

130 MHz to 1 GHz 4

SAE EMI Level 2 -

DS9178 Rev 4 87/96

STM8L051F3 Electrical parameters

Static latch-up

•LU: 3 complementary static tests are required on 6 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

Table 50. ESD absolute maximum ratings

Symbol Ratings Conditions Maximum

value (1)

1. Guaranteed by characterization results.

Unit

VESD(HBM) Electrostatic discharge voltage

(human body model)

TA = +25 °C

2000

VESD(CDM) Electrostatic discharge voltage

(charge device model) 500

Table 51. Electrical sensitivities

Symbol Parameter Class

LU Static latch-up class II

Package characteristics STM8L051F3

88/96 DS9178 Rev 4

9 Package characteristics

9.1 ECOPACK®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

HHHHHHHHHH ¥ E 2% HHHHHHHHHL : \ T ETD, I f -4 .LL

DS9178 Rev 4 89/96

STM8L051F3 Package characteristics

9.2 Package mechanical data

9.3 TSSOP20 package information

Figure 38. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package outline

1. Drawing is not to scale.

Table 52. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package mechanical data

Symbol

millimeters inches(1)

Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472

A1 0.050 - 0.150 0.0020 - 0.0059

A2 0.800 1.000 1.050 0.0315 0.0394 0.0413

b 0.190 - 0.300 0.0075 - 0.0118

c 0.090 - 0.200 0.0035 - 0.0079

D(2) 6.400 6.500 6.600 0.2520 0.2559 0.2598

E 6.200 6.400 6.600 0.2441 0.2520 0.2598

E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772

e - 0.650 - - 0.0256 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0° - 8° 0° - 8°

aaa - - 0.100 - - 0.0039

YA_ME_V3

EE1

aaa

SEATING

PLANE

CGAUGE PLANE

0.25 mm

PIN 1

IDENTIFICATION

j A DUDHUDHUHD LJ Jg

Package characteristics STM8L051F3

90/96 DS9178 Rev 4

Figure 39. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,

package footprint

1. Dimensions are expressed in millimeters.

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs

shall not exceed 0.15mm per side.

3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not

exceed 0.25mm per side.

YA_FP_V1

7.10 4.40

0.25

6.25

1.35

0.40 0.65

1.35

20 11

DS9178 Rev 4 91/96

STM8L051F3 Package characteristics

Device marking for TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm,

0.65 mm pitch

The following figure gives an example of topside marking orientation versus pin 1/ball A1

identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 40. Device marking for TSSOP20 – 20-lead thin shrink small outline,

6.5 x 4.4 mm, 0.65 mm pitch example

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv17034v1

8L051F3P6

R Y WW

Product identification

Additional information

Date code

Unmarkable surface

PIN1 reference

Package characteristics STM8L051F3

92/96 DS9178 Rev 4

9.4 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 15: General operating conditions on page 48.

The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using

the following equation:

TJmax = TAmax + (PDmax x Θ

JA)

Where:

•TAmax is the maximum ambient temperature in °C

•Θ

JA is the package junction-to-ambient thermal resistance in °C/W

•PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

•PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip

internal power.

•PI/Omax represents the maximum power dissipation on output pins

Where:

PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*I OH),

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in

the application.

Table 53. Thermal characteristics(1)

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

Symbol Parameter Value Unit

Thermal resistance junction-ambient

TSSOP20 110 °C/W

DS9178 Rev 4 93/96

STM8L051F3 Ordering information

10 Ordering information

Figure 41. Low density value line STM8L051F3 ordering information scheme

STM8 L 051 F 3 P 6

Product class

STM8 microcontroller

Pin count

F = 20 pins

Package

P = TSSOP

Example:

Sub-family type

051 = Ultra-low-power

Family type

L = Low power

Temperature range

6 = – 40 to 85 °C

For a list of available options (such as memory size, package) and orderable part numbers or for

further information on any aspect of this device, please contact the ST sales office nearest to you.

Program memory size

3 = 8 Kbytes

Revision history STM8L051F3

94/96 DS9178 Rev 4

11 Revision history

Table 54. Document revision history

Date Revision Changes

01-Aug-2012 1 Initial release.

26-Mar-2014 2

Updated TSS0P20 package information

Updated pin name related to pin1 and 2 inside Table 4: STM8L051F3

pin description

Updated inside Table 10: Option byte addresses OPT5 default factory

of BOR to 0x00

04-Jul-2017 3

Updated

– All document to refer to specific RPN instead to the whole Value line

when relevant to make content clearer

– Document’s title

– Footnotes were standardized on Section 8: Electrical parameters

– Figure on Features on the cover page

–Section 1: Introduction

–Section 2: Description

–Section 2.2: Ultra-low-power continuum

–Section 8.2: Absolute maximum ratings

–Section 9.3: TSSOP20 package information

–Figure 1: STM8L051F3 block diagram

–Figure 2: STM8L051F3 clock tree diagram

–Figure 5: Pin loading conditions

–Figure 6: Pin input voltage

–Figure 8: Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz

–Figure 9: Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1)

–Figure 10: Typ. IDD(LPR) vs. VDD (LSI clock source)

–Figure 11: Typ. IDD(LPW) vs. VDD (LSI clock source)

–Figure 13: LSE oscillator circuit diagram

–Figure 15: Typical LSI frequency vs. VDD

–Figure 16: Typical VIL and VIH vs VDD (high sink I/Os)

–Figure 17: Typical VIL and VIH vs VDD (true open drain I/Os)

–Figure 18: Typical pull-up resistance RPU vs VDD with VIN=VSS

–Figure 19: Typical pull-up current Ipu vs VDD with VIN=VSS

–Figure 29: SPI1 timing diagram - slave mode and CPHA=0

–Figure 30: SPI1 timing diagram - slave mode and CPHA=1(1)

–Figure 34: Typical connection diagram using the ADC

–Figure 35: Maximum dynamic current consumption on VREF+ supply

pin during ADC conversion

DS9178 Rev 4 95/96

STM8L051F3 Revision history

04-Jul-2017 3

(Cont.)

Updated (continuation):

–Figure 37: Power supply and reference decoupling (VREF+

connected to VDDA)

–Figure 38: TSSOP20 – 20-lead thin shrink small outline, 6.5 x

4.4 mm, 0.65 mm pitch, package outline

–Figure 39: TSSOP20 – 20-lead thin shrink small outline, 6.5 x

4.4 mm, 0.65 mm pitch, package footprint

–Table 25: Current consumption under external reset

Added

–Section : Device marking for TSSOP20 – 20-lead thin shrink small

outline, 6.5 x 4.4 mm, 0.65 mm pitch

–Figure 40: Device marking for TSSOP20 – 20-lead thin shrink small

outline, 6.5 x 4.4 mm, 0.65 mm pitch example

07-Sep-2018 4

Updated:

–12-bit ADC up to 1 Msps/10 channels feature on cover page

–Section 3.8: Analog-to-digital converter

–Table 4: STM8L051F3 pin description

–Table 7: General hardware register map

–Table 43: ADC1 characteristics

–Table 47: RAIN max for fADC = 16 MHz

– Added introduction to following sections:

Section 3.2: Central processing unit STM8

Section 3.3: Reset and supply management

Section 3.13: Communication interfaces

Section 3.15: Development support

Section 5: Memory and register map

Section 6: Interrupt vector mapping

Section 8: Electrical parameters

Section 8.3.1: General operating conditions

Section 8.3.2: Embedded reset and power control block

characteristics

Table 54. Document revision history

Date Revision Changes

STM8L051F3

96/96 DS9178 Rev 4

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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