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© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 9
1Publication Order Number:
MC14514B/D
MC14514B, MC14515B
4-Bit Transparent Latch /
4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R−S type flip−flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4−bit latch / 4 to 16 line decoder are
constructed with N−channel and P−channel enhancement mode
devices in a single monolithic structure. The latches are R−S type
flip−flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
Features
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout −0.5 to VDD
+0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout ±10 mA
Power Dissipation per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
xx = 14 or 15
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
MARKING DIAGRAM
1
24
SOIC−24
DW SUFFIX
CASE 751E
145xxB
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
S5
S7
D2
D1
ST
S3
S4
S6 S10
D3
D4
INH
VDD
S15
S14
S9
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
S13
S12
S8
S11
S0
VSS
S2
S1
PIN ASSIGNMENT
2:31:23:
MC14514B, MC14515B
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2
Data Inputs Selected Output
MC14514 = Logic “1”
Inhibit D C B A MC14515 = Logic “0”
00000 S0
00001 S1
00010 S2
00011 S3
00100 S4
00101 S5
00110 S6
00111 S7
01000 S8
01001 S9
0 1 0 1 0 S10
01011 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs = 0, MC14514
All Outputs = 1, MC14515
DECODE TRUTH TABLE (Strobe = 1)*
X = Don’t Care
*Strobe = 0, Data is latched
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
4 TO 16
DECODER
TRANSPARENT
LATCH
STROBE
INHIBIT
2
3
1
21
22
23
DATA 1
DATA 2
DATA 3
DATA 4
A
B
C
D20
17
18
4
5
6
7
8
10
9
11
19
16
13
14
15
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C DS15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
ORDERING INFORMATION
Device Package Shipping†
MC14514BDWR2G SOIC−24
(Pb−Free) 1000 / Tape & Reel
NLV14514BDWR2G*
MC14515BDWR2G SOIC−24
(Pb−Free) 1000 / Tape & Reel
NLV14515BDWR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14514B, MC14515B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH 5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
mAdc
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current Iin 15 −±0.1 −±0.00001 ±0.1 −±1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF
Quiescent Current (Per Package) IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
ITL 5.0
10
15
IT = (1.35 mA/kHz) f + IDD
IT = (2.70 mA/kHz) f + IDD
IT = (4.05 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
MC14514B, MC14515B
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4
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD
All Types
Unit
Min
Typ
(Note 6) Max
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH 5.0
10
15
−
−
−
180
90
65
360
180
130
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time; Data, Strobe to S
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.86 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
−
−
−
550
225
150
1100
450
300
ns
Inhibit Propagation Delay Times
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 117 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL 5.0
10
15
−
−
−
400
150
100
800
300
200
ns
Setup Time Data to Strobe tsu 5.0
10
15
250
100
75
125
50
38
−
−
−
ns
Hold Time Strobe to Data th5.0
10
15
– 20
0
10
– 100
– 40
– 30
−
−
−
ns
Strobe Pulse Width tWH 5.0
10
15
350
100
75
175
50
38
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Drain Characteristics Test Circuit
EXTERNAL
POWER SUPPLY
VSS
STROBE
INHIBIT
D1
D2
D3
D4
VDD
VDS
ID
For MC14515B
1. For P−channel: Inhibit = VDD
2. For N−channel: Inhibit = VSS
2. and D1−D4 constitute binary
2. code for “output under test.”
For MC14514B
1. For P−channel: Inhibit = VSS
1. and D1−D4 constitute
1. binary code for “output
1. under test.”
2. For N−channel: Inhibit = VDD
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
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MC14514B, MC14515B
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5
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
CL
CL
VDD
VDD
VSS
S0
S15
12
24
ID
0.01 mF
CERAMIC
500
mF
VDD
VSS
Vin
20 ns 20 ns
90%
10%
STROBE
D1
D2
D3
D4
INHIBIT
Figure 3. Switching Time Test Circuit and Waveforms
PROGRAMMABLE
PULSE
GENERATOR
VDD
STROBE
INHIBIT
D1
D2
D3
D4
CL
VDD
VSS
VDD
VSS
S0
S1
S15
VSS
CL
CL
INPUT
OUTPUT
tTLH
tTLH tTHL
tTHL
tPHL
tPLH
20 ns
OUTPUT S0
OUTPUT S1
OUTPUT S15
90%
50%
10%
90%
50%
10%
hllp://onsemi.com
6
MC14514B, MC14515B
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6
LOGIC DIAGRAM
DATA 1 2
DATA 2 3
DATA 3 21
DATA 4 22
STROBE 1
INHIBIT 23
Q
QR
S
Q
QR
S
Q
QR
S
Q
QR
S
A
B
C
D
IN MC14515B ONLY
AB C D
11 S0
9S1
10 S2
8S3
7S4
6S5
5S6
4S7
18 S8
17 S9
20 S10
19 S11
14 S12
13 S13
16 S14
15 S15
AB C D
ABCD
AB CD
A B CD
AB CD
ABCD
AB CD
A B C D
AB C D
ABCD
AB CD
ABCD
AB CD
ABCD
AB CD
MC14514B, MC14515B
http://onsemi.com
7
COMPLEX DATA ROUTING
Two MC14512 eight−channel data selectors are used here
with the MC14514B four−bit latch/decoder to effect a
complex data routing system. A total of 16 inputs from data
registers are selected and transferred via a 3−state data bus
to a data distributor for rearrangement and entry into 16
output registers. In this way sequential data can be re−routed
or intermixed according to patterns determined by data
select and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3−state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
times faster then the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be
transferred to the data bus before the next most significant
bit is presented for transfer by the input registers.
Information from the 3−state bus is redistributed by the
MC14514B four−bit latch/decoder. Using the four−bit
address, D1 thru D4, the information on the inhibit line can
be transferred to the addressed output line to the desired
output registers, A thru P. This distribution of data bits to the
output registers can be made in many complex patterns. For
example, all of the most significant bits from the input
registers can be routed into output register A, all of the next
most significant bits into register B, etc. In this way
horizontal, vertical, or other methods of data slicing can be
implemented.
DATA ROUTING SYSTEM
INPUT
REGISTERS
DATA
TRANSFER
DATA
DISTRIBUTION
OUTPUT
REGISTERS
3-STATE
DATA BUS
REGISTER A
REGISTER P
REGISTER 1
REGISTER 8
REGISTER 9
REGISTER 16
DATA
SELECT
STROBE
INHIBIT
DIS
DIS
Q
Q
D1 D2 D3 D4
A0 A1 A2
A0 A1 A2
MC14514B
MC14512MC14512
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
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SIDE VIEW END v
RECOMMENDED
SOLDERING FOOTFH
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MC14514B, MC14515B
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8
PACKAGE DIMENSIONS
SOIC−24 WB
CASE 751E−04
ISSUE F
b
M
0.25 C
SEATING
PLANE
A1
M
L
DETAIL A
END VIEW
h_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED
BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
NOTE 3
PIN 1
12
1
24 13
TOP VIEW DIM MIN MAX
MILLIMETERS
A2.35 2.65
b0.35 0.49
e1.27 BSC
h0.25 0.75
c0.23 0.32
A1 0.13 0.29
L0.41 0.90
M0 8
__
D
E1
SIDE VIEW
11.00
24X
0.52
24X
1.62
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
E10.30 BSC
RECOMMENDED
INDICATOR A B
0.25 C
24X
B
A
C
A
NOTE 5
x 45
c
NOTE 3 DETAIL A
C
H
D15.25 15.54
E1 7.40 7.60
E
S S
e
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MC14514B/D
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